Results 161 to 170 of about 769 (247)
Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights
This work demonstrates an energy‐efficient on‐chip learning system using an Metal‐Ferroelectric‐Insulator‐Semiconductor FeAND synaptic array. By employing a feedback alignment scheme with a separate backward array using fixed random weights, the system overcomes directional limitations of AND‐type arrays and achieves robust, low‐power learning suitable
Minsuk Song +8 more
wiley +1 more source
Neuromorphic chips for biomedical engineering. [PDF]
Wang K +5 more
europepmc +1 more source
A volatile‐switching compact model of electrochemical metallization memory cells for neuromorphic architecture is developed and validated by reliable reproduction of device characterization measurements: I−V sweeps, SET kinetics, relaxation dynamics.
Rana Walied Ahmad +4 more
wiley +1 more source
Digital coding metamaterials with multi-modulation schemes and beam steering for intra-chip millimeter-wave connectivity. [PDF]
Shen Z, Taravati S, Yan J.
europepmc +1 more source
Modular Electronic Microrobots With Onboard Sensor‐Program‐Steered Locomotion
Modular electronic smartlet microrobots integrate ambient‐light energy harvesting, photodetection, programmable CMOS control, and bubble‐based actuation within a sub‐millimeter fold‐up architecture. A 58‐bit on‐board CMOS chiplet enables sensor–program steered switching between independently addressable actuators, achieving closed‐loop 2D navigation in
Vineeth K. Bandari +6 more
wiley +1 more source
Synthesis of Programmable Bioelectronic Yeast for Biohybrid Futures. [PDF]
Erpf PE +5 more
europepmc +1 more source
A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song +21 more
wiley +1 more source
Applicability and Design Considerations of Chaotic and Quantum Entropy Sources for Random Number Generation in IoT Devices. [PDF]
Marszalek W +3 more
europepmc +1 more source
This article introduces an input sparsity‐aware computing‐in‐memory macro featuring novel bidirectional conversion‐skippable analog‐to‐digital converters. By dynamically adjusting resolution based on element‐level sparsity, the architecture skips redundant most significant bit and least significant bit conversions.
Choongseok Song +2 more
wiley +1 more source
Actor-critic networks with analogue memristors mimicking reward-based learning. [PDF]
Portner K +17 more
europepmc +1 more source

