Results 181 to 190 of about 557 (199)

Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

Proceedings International Test Conference 1996. Test and Design Validity, 2002
A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout by investigating typical "local" layout structures of analogue designs.
openaire   +1 more source

<title>Linearisation for analogue optical links using integrated CMOS predistortion circuits</title>

SPIE Proceedings, 2005
Fu-Chuan Lin, David M. Holburn
openaire   +1 more source

Electrical characterization of analogue and RF integrated circuits by thermal measurements

Microelectronics Journal, 2007
Diego Mateo, Josep Altet
exaly  

CMOS compatible high-voltage compliant MESFET-based analogue IC building blocks

Electronics Letters, 2009
T J Thornton
exaly  

The Design of CMOS Radio-Frequency Integrated Circuits

Microelectronics International, 2004
exaly   +4 more sources

Sizing Analogue Integrated Circuits by Integer Encoding and NSGA-II

IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India), 2018
Esteban Tlelo-Cuautle
exaly  

Linearisation for analogue optical links using integrated CMOS predistortion circuits

2005
David M Holburn
exaly  

Advanced layout techniques for high‐speed analogue circuits in 28 nm HKMG CMOS process

Electronics Letters, 2018
exaly  

CMOS amplifier designs for Josephson-CMOS interface circuits

IEEE Transactions on Applied Superconductivity, 1995
T Van Duzer
exaly  

The influence of No Fault Found in analogue CMOS circuits

2014
Hans G Kerkhoff, Jinbo Wan
exaly