Novel readout circuit architecture for CMOS image sensors minimizing RTS noise [PDF]
, 2011 This letter presents a novel readout architecture and its associated readout sequence for complementary metal–oxide– semiconductor (CMOS) image sensors (CISs) based on switch biasing techniques in order to reduce noisy pixel numbers induced by in-pixel
Philippe Martin-Gonthier +3 more
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Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime
ETRI Journal, 2019 The p‐type nanowire field‐effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in‐depth technology computer‐aided design (TCAD) with quantum models for sub‐10‐nm advanced logic technology.
Eunseon Yu +7 more
doaj +1 more source
Design and Applications of Integrated Transducers in Commercial CMOS Technology
Frontiers in Mechanical Engineering, 2022 Monolithic integration of Microelectromechanical Systems (MEMS) directly within CMOS technology offers enhanced functionality for integrated circuits (IC) and the potential improvement of system-level performance for MEMS devices in close proximity to ...
Udit Rawat +2 more
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Research-grade CMOS image sensors for remote sensing applications [PDF]
, 2004 Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle.
Belliot, Pierre +8 more
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IEEE Access, 2020 As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications.
Yang Wang +5 more
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Low power domino logic circuits in deep-submicron technology using CMOS
Engineering Science and Technology, an International Journal, 2018 Leakage power and propagation delay are the two major challenges in designing CMOS VLSI circuits, in deep sub-micron technology. This paper proposes a novel technique: Foot Driven Stack Transistor Domino Logic (FDSTDL) for designing CMOS domino logic ...
Sandeep Garg, Tarun Kumar Gupta
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An Extended CMOS ISFET Model Incorporating the Physical Design Geometry and the Effects on Performance and Offset Variation [PDF]
, 2011 17/04/13 meb. Accepted version OK to pub.This paper presents an extended model for the CMOS-based Ion-Sensitive-Field-Effect-Transistor (ISFET), incorporating design parameters associated with the physical geometry of the device.
Liu, Y +14 more
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Optoelectrical performance evolution of CMOS image sensors exposed to gamma radiation [PDF]
, 2009 In this paper we present a study of ionizing radiation effects, up to 5 kGy, in several CMOS image sensors manufactured using a commercial 0.18 μm technology dedicated to ...
Goiffon, Vincent +2 more
core
A digital high-dynamic-range CMOS image sensor with multi-integration and pixel readout request [PDF]
, 2007 A novel principle has been developed to build an ultra wide dynamic range digital CMOS image sensor. Multiple integrations are used to achieve the required dynamic.
Segura, Josep +7 more
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SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology
IEEE Journal of the Electron Devices Society, 2022 Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600V lateral SiC power MOSFETs and low-voltage SiC CMOS devices.
Tianshi Liu +9 more
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