Results 41 to 50 of about 7,631,832 (303)

Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

IEEE Access, 2020
As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications.
Yang Wang, Xiangliang Jin, Yan Peng, Jun Luo, Zeyu Zhong, Jun Yang   +5 more
doaj   +1 more source

All‐in‐One Analog AI Hardware: On‐Chip Training and Inference with Conductive‐Metal‐Oxide/HfOx ReRAM Devices

Advanced Functional Materials, EarlyView.
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone, Victoria Clerico, Wooseok Choi, Tommaso Stecconi, Folkert Horst, Laura Bégon‐Lours, Matteo Galetta, Antonio La Porta, Nikhil Garg, Fabien Alibart, Bert Jan Offrein, Valeria Bragaglia   +11 more
wiley   +1 more source

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

IEEE Journal of the Electron Devices Society, 2022
Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600V lateral SiC power MOSFETs and low-voltage SiC CMOS devices.
Tianshi Liu, Hua Zhang, Sundar Babu Isukapati, Emran Ashik, Adam J. Morgan, Bongmook Lee, Woongje Sung, Ayman Fayed, Marvin H. White, Anant K. Agarwal   +9 more
doaj   +1 more source

Control of Polarization and Polar Helicity in BiFeO3 by Epitaxial Strain and Interfacial Chemistry

Advanced Functional Materials, EarlyView.
In BiFeO3 thin films, the interplay of interfacial chemistry, electrostatics, and epitaxial strain is engineered to stabilize homohelicity in polarization textures at the domain scale. The synergistic use of a Bi2O2‐terminated Aurivillius buffer layer and a highly anisotropic compressive epitaxial strain offers new routes to control the polar‐texture ...
Elzbieta Gradauskaite, Lilia Huynh, Natascha Gray, Quintin N. Meier, Marta D. Rossell, Morgan Trassin   +5 more
wiley   +1 more source

Design and Simulation of Reversible Logic Gate Using HCS Macro-Model

Memories - Materials, Devices, Circuits and Systems
—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc.
Snigdha Chowdhury Kolay, Amrita Chatterjee, Subrata Chattopadhyay   +2 more
doaj   +1 more source

New structure transistors for advanced technology node CMOS ICs

National Science Review
Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations in transistors.
Qingzhu Zhang, Yongkui Zhang, Yanna Luo, H. Yin   +3 more
semanticscholar   +1 more source

Integration of Low‐Voltage Nanoscale MoS2 Memristors on CMOS Microchips

Advanced Functional Materials, EarlyView.
This article presents the first monolithic integration of nanoscale MoS2‐based memristors into the back‐end‐of‐line of foundry‐fabricated CMOS microchips in a one‐transistor‐one‐resistor (1T1R) architecture. The MoS2‐based 1T1R cells exhibit forming‐free, nonvolatile resistive switching with ultra‐low operating voltages, low cycle‐to‐cycle variability ...
Jimin Lee, Sofía Cruces, Xiaohua Liu, Yang Chen, Vasilis A. Maroufidis, Janghyun Jo, Lukas Völkel, Dennis Braun, Michael Möller, Leon Brackmann, Holger Kalisch, Michael Heuken, Andrei Vescan, Rafal E. Dunin‐Borkowski, Joachim Mayer, Stefan Wiefels, Max C. Lemme   +16 more
wiley   +1 more source

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Nanomaterials
After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In
H. Radamson, Yuanhao Miao, Ziwei Zhou, Zhenhua Wu, Z. Kong, Jianfeng Gao, Hong Yang, Yuhui Ren, Yongkui Zhang, Jiangliu Shi, Jinjuan Xiang, Hushan Cui, Bin Lu, Junjie Li, Jinbiao Liu, Hongxiao Lin, Haoqing Xu, Mengfan Li, Jiaji Cao, Chuangqi He, Xiangyang Duan, Xuewei Zhao, Jiale Su, Yong Du, Jiahan Yu, Yuanyuan Wu, Miao Jiang, Di Liang, Ben Li, Yan Dong, Guilei Wang   +30 more
semanticscholar   +1 more source

Optoelectronic Synaptic Devices Using Molecular Telluride Phase‐Change Inks for Three‐Factor Learning

Advanced Functional Materials, EarlyView.
Optoelectronic synaptic devices based on solution‐processed molecular telluride GST‐225 phase‐change inks are demonstrated for three‐factor learning. A global optical signal broadcast through a silicon waveguide induces non‐volatile conductance updates exclusively in locally electrically flagged memristors.
Kevin Portner, Dhananjeya Kumaar, Giacomo Torti, Killian Keller, Till Zellweger, Florian M. Schenk, Christoph Weilenmann, Daniel Chelladurai, Vara Prasad Jonnalagadda, Ghazi Sarwat Syed, Vanessa Wood, Jürg Leuthold, Alexandros Emboras, Maksym Yarema, Mathieu Luisier   +14 more
wiley   +1 more source

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Journal of Electrical and Computer Engineering, 2011
This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase ...
Ni Xu, Woogeun Rhee, Zhihua Wang
doaj   +1 more source