Results 181 to 190 of about 4,444 (239)

Synthesis of a CNTFET-Based Ternary Full Adder Using a Carry-Less Ternary Half Adder

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The full adder (FA) is an essential element within arithmetic units, significantly contributing to their computational efficiency. Contemporary research endeavors are actively exploring optimized FA circuit designs.
S. Haq, Erfan Abbasian, Maedeh Orouji, Sajad A. Loan, Tabassum Khurshid   +4 more
semanticscholar   +1 more source

Hybrid MTJ/CNTFET-Based Binary Synapse and Neuron for Process-in-Memory Architecture

IEEE Magnetics Letters, 2023
This letter develops a reliable, integrated binary synapse and neuron model for hardware implementation of binary neural networks. Thanks to the nonvolatile nature of magnetic tunnel junctions and the unique features of carbon nanotube field-effect ...
Milad Tanavardi Nasab, Arefe Amirany, M. H. Moaiyeri, Kian Jafari   +3 more
semanticscholar   +1 more source

A resilient, high-performance, low-power 11T CNTFET SRAM cell for IoT implementations

Physica Scripta
Current system-on-chips need robust, economical SRAM cells since energy sources are limited and technology is scaling. Hence, a resilient, delay and energy-optimized 11T CNTFET SRAM design is suggested in this analysis.
J. S, R. P., M. Pushpa, S. Subhashini, U. Jeethika   +4 more
semanticscholar   +1 more source

Performance study of 12-CNTFET and GDI CNTFET based full adder in HSPICE

2014 International Conference on Advances in Engineering & Technology Research (ICAETR - 2014), 2014
This manuscript reports and analyzes 12-CNTFET and GDI CNTFET based full adder implementation at 32 nm level. As figures of merit, stability, power dissipation and Power Delay Product (PDP) are considered for the best overall performance. Intensive HSPICE simulations have been performed to investigate the distribution of the power and delay of the ...
null Habib Muhammad Nazir Ahmad, null Mohammad Shafquatul Islam, null Kazi Muhammad Jameel, null Arman Riaz Ochi, Rakibul Hafiz   +4 more
openaire   +1 more source

A CNTFET-Based 10T Static Memory Design Immune to Read and Half-Select Disturbs for Low-Power Wearable Biomedical Systems

IEEE Access
This paper introduces a novel 10T SRAM cell optimized for low-power, high-reliability biomedical wearable systems. The proposed design features a read-assist mechanism to suppress read disturbs, enhancing read static noise margin (RSNM), while a ...
Shams Ul Haq, Erfan Abbasian, Imran Ahmed Khan, Owais Ahmad Shah, Arun Balodi, M. Tolani, V. B. Sreenivasulu   +6 more
semanticscholar   +1 more source

Novel design of power-efficient quaternary logic gates using CNTFET

International Journal of Electronics, 2023
This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard ...
Anisha Paul, B. Pradhan
semanticscholar   +1 more source

A Novel Low-Complexity Power-Efficient Design of Standard Ternary Logic Gates using CNTFET

2023 International Conference on Computer, Electrical & Communication Engineering (ICCECE), 2023
This paper introduces novel low-complexity and power-efficient designs of standard ternary (ST) logic gates like the standard ternary inverter (STI), NAND (STNAND), NOR (STNOR), and XOR (STXOR) gates, along with the ternary minimum (TMIN) and ternary ...
Anisha Paul, B. Pradhan
semanticscholar   +1 more source

Ternary SRAM circuit designs with CNTFETs

International Journal of Circuit Theory and Applications, 2023
SummaryStatic random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues.
Abdelrahman, Doaa, Fouda, Mohammed, Alouani, Ihsen, Said, Lobna, Radwan, Ahmed   +4 more
openaire   +2 more sources

Low-Power High-Speed CNTFET-based 1-bit Comparator Design using CCT and STT Techniques

2023 Second International Conference on Electronics and Renewable Systems (ICEARS), 2023
Carbon Nanotube Field Effect Transistor (CNTFET) based VLSI circuits are now desired due to low power and reduced chip area-which are in great demand in the VLSI realm.
Ricky Rajora, K. Sharma, Lipika Gupta, Ashish Sachdeva, Avinash Sharma   +4 more
semanticscholar   +1 more source

CNTFET-based logic circuit design

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., 2006
This paper gives an overview of some potential uses of carbon nanotube field effect transistors (CNTFETs) in logic circuit design. The realization of existing logic functions with resistive-load and complementary logic is described, with some examples of how a logic function can be coded by selective doping of a single nanotube molecule.
I. O'Connor, J. Liu, F. Gaffiot
openaire   +1 more source