Results 71 to 80 of about 290,773 (308)

A Q‐Learning Algorithm to Solve the Two‐Player Zero‐Sum Game Problem for Nonlinear Systems

International Journal of Adaptive Control and Signal Processing, Volume 39, Issue 3, Page 566-581, March 2025.
A Q‐learning algorithm to solve the two‐player zero‐sum game problem for nonlinear systems. ABSTRACT This paper deals with the two‐player zero‐sum game problem, which is a bounded L2$$ {L}_2 $$‐gain robust control problem. Finding an analytical solution to the complex Hamilton‐Jacobi‐Issacs (HJI) equation is a challenging task.
Afreen Islam, Anthony Siming Chen, Guido Herrmann   +2 more
wiley   +1 more source

Analytical Capacitance Model for Carbon Nanotube Field-Effect Transistors Including Interface-Trap Effects

Nanomaterials
The creation of carbon nanotubes has sparked a paradigm shift in the post-silicon era because of their decent electronic and optical properties. However, interface traps pose an obstacle in the realization of high-performance carbon nanotube field-effect
Bin Zhou, Rui Zhan, Zilin Teng, Yiheng Xue, Xiaoyan Hu, Jianhua Jiang, Panpan Zhang   +6 more
doaj   +1 more source

Revisiting Stability Criteria in Ball‐Milled High‐Entropy Alloys: Do Hume–Rothery and Thermodynamic Rules Equally Apply?

Advanced Engineering Materials, Volume 27, Issue 6, March 2025.
The stability criteria affecting the formation of high‐entropy alloys, particularly focusing in supersaturated solid solutions produced by mechanical alloying, are analyzed. Criteria based on Hume–Rothery rules are distinguished from those derived from thermodynamic relations. The formers are generally applicable to mechanically alloyed samples.
Javier S. Blázquez, Alejandro F. Manchón‐Gordón, Antonio Vidal‐Crespo, Rafael Caballero‐Flores, Jhon J. Ipus, Clara F. Conde   +5 more
wiley   +1 more source

CJM: A Compact Model for Double-Gate Junction FETs

IEEE Journal of the Electron Devices Society, 2019
The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-
Nikolaos Makris, Matthias Bucher, Farzan Jazaeri, Jean-Michel Sallese   +3 more
doaj   +1 more source

Low‐Cost, Large‐Scale Nanoporous Metals by Mechanical Alloying, Oxide Reduction, and Dealloying of Powders

Advanced Engineering Materials, EarlyView.
Powder metal processing provides scalable advantages in nanoporous (np) metal development. Mechanical alloying is used to produce unique precursors for hybrid nanopore formation by oxide reduction and dealloying. As demonstrated in np Ag, this approach improves process efficiency while promoting smaller ligaments and larger pores, both of which are ...
Mark A. Atwater, Oliver A. Fowler
wiley   +1 more source

MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Analogue Circuit Simulation

, 2004
In this paper, we present a compact model for silicon-on-insulator (SOI) laterally double diffused (LD) MOSFETs. The model is complete insofar as it uses no subcircuits, and is intended to predict device operation in all regions of bias.
Swanenberg, M., Mistry, K., Redman-White, W., Benson, J., D'Halleweyn, N.V.T.   +4 more
core  

Current-Voltage Modeling of Transistors Based on Two-Dimensional Molybdenum Disulfide

IEEE Access
This paper presents a compact model for the current-voltage (I–V) characteristics of field-effect transistors (FETs) based on two-dimensional molybdenum disulfide (MoS2) channels. The proposed model is fully analytical, explicit, and physics-based,
Adelcio M. de Souza, Daniel R. Celino, Regiane Ragi, Murilo A. Romero   +3 more
doaj   +1 more source

Planar Solid‐State Nanopores Toward Scalable Nanofluidic Integration Based on CMOS Technology

Advanced Engineering Materials, EarlyView.
We present a scalable silicon‐based fabrication strategy for planar solid‐state nanopores to enable their integration with complex nanofluidic systems. Prototype devices demonstrate normal voltage‐current characteristics, good noise performance, and appreciable streaming currents. Our CMOS‐compatible fabrication process offers precise geometric control
Ngan Hoang Pham, Chenyu Wen, Mohammad Hadi Khaksaran, Won‐Yong Lee, Javier Cruz, Klas Hjort, Dongping Wu, Shi‐Li Zhang   +7 more
wiley   +1 more source

A Physically Based Relation Between Extracted Threshold Voltage and Surface Potential Flat-Band Voltage for MOSFET Compact Modeling

, 2001
Compact MOS models based on surface potential are now firmly established, but for practical applications there is no reliable link between measured values of threshold voltage and the flat-band voltage on which such models are based.
Easson, Craig A., Pelloie, Jean-Luc, Benson, James, Redman-White, William, D'Halleweyn, Nele V., Faynot, Olivier, Uren, Michael J.   +6 more
core  

A Compact Model Based on Bardeen’s Transfer Hamiltonian Formalism for Silicon Single Electron Transistors

IEEE Access, 2019
Presented is a physics-based compact model for a silicon-nanopillar single-electron transistor (SET). Tunneling currents are calculated using a master equation approach with rates obtained via the transfer Hamiltonian formalism.
Fabian J. Klupfel
doaj   +1 more source