Results 251 to 260 of about 25,106,713 (303)
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Compact Modeling of Perpendicular STT-MTJs With Double Reference Layers
IEEE transactions on nanotechnology, 2019This paper shows the steps to set up a simulation framework for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) with double-barrier and two antiparallel reference layers (DMTJs).
Raffaele De Rose +5 more
semanticscholar +1 more source
Frustrated Models for Compact Packings
1998We review some properties of frustrated models which reproduce the logaritmic relaxation in granular compaction.
A. Coniglio +4 more
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COMPACT A Reclamation Soil Compaction Model Part I. Model Development
Transactions of the ASAE, 1992A physically based, event oriented soil compaction model, known as COMPACT, was developed as a management or research tool to evaluate the effect of surface mining systems on compaction of soil material during reclamation. Simulation of compaction throughout the soil profile at a surface mining reclamation site requires information describing how ...
null R. L. Bingner, null L. G. Wells
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Analytical Compact Model for PMUTs Interfaces
2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018Piezoelectric Micromachined ultrasound transducers (PMUT) have been studied extensively in the last few years, with a focus on the transducer fabrication or application driven front-end interface. This paper presents an analytical approach that addresses PMUTs along with their front-end interfaces.
Bedier, Mohammed +2 more
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IEEE Transactions on Electron Devices, 2018
This paper presents a detailed analysis of the time dynamics of the gate-induced drain leakage (GIDL)-assisted increase of the string potential in vertical-channel 3-D NAND Flash arrays.
G. Malavena +3 more
semanticscholar +1 more source
This paper presents a detailed analysis of the time dynamics of the gate-induced drain leakage (GIDL)-assisted increase of the string potential in vertical-channel 3-D NAND Flash arrays.
G. Malavena +3 more
semanticscholar +1 more source
Negative-Capacitance FinFETs: Numerical Simulation, Compact Modeling and Circuit Evaluation
International Conference on Simulation of Semiconductor Processes and Devices, 2018A complete simulation framework is presented for Negative Capacitance FinFETs including Numerical Simulation, Compact Modeling, and Circuit Evaluation.
J. Duarte +11 more
semanticscholar +1 more source
The Synergy SPICE – Compact Models
ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), 2019SPICE became the de facto standard Integrated Circuit (IC) design tool due in part to being an open-source software program and incorporating mathematical models for the behavior of the semiconductor devices at the core of ICs. The chosen detail level of the device equations in these models is appropriate for circuit simulation and they are referred to
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Compact Modeling of Drain Current in Double Gate Negative Capacitance MFIS Transistor
International Conference on E-Business and E-Government, 2018A surface potential based compact model for a long channel MFIS (Metal-Ferroelectric-Insulator-Semiconductor) type Double Gate Negative Capacitance transistor (DG-NCFET) is presented in this paper.
A. Gaidhane +3 more
semanticscholar +1 more source
On Compact Storage Models for Gazetteers
2006This paper describes compact storage models for gazetteers using state-of-the-art finite-state technology. In particular, we compare the standard method based on numbered indexing automata associated with an auxiliary storage device, against a pure finite-state representation, the latter being superior in terms of space and time complexity, when ...
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Compact Language Models via Pruning and Knowledge Distillation
Neural Information Processing SystemsLarge language models (LLMs) targeting different deployment scales and sizes are currently produced by training each variant from scratch; this is extremely compute-intensive.
Saurav Muralidharan +8 more
semanticscholar +1 more source

