Results 21 to 30 of about 1,373,407 (260)
Expansible Network-on-Chip Architecture
Advances in Electrical and Computer Engineering, 2018 Interconnection has a great importance to provide a high bandwidth communication among parallel systems. On multi-core context, Network-on-Chip is the default intra-chip interconnection choice, providing low contention and high bandwidth between the ...
PIRES, I. L. P. +2 more
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The Prism Bridge: Maximizing Inter-Chip AXI Throughput in the High-Speed Serial Era
IEEE Access, 2023 In this paper, we present the Prism Bridge, a soft IP core developed to bridge FPGA-MPSoC systems using high-speed serial links. Considering the current trend of ubiquitous serial transceivers with staggeringly increasing line rates, minimizing overhead ...
Robert Drehmel, Hans-Ulrich Heiss
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Practical Verifiable Computation by Using a Hardware-Based Correct Execution Environment
IEEE Access, 2020 The verifiable computation paradigm has been studied extensively as a means to verifying the result of outsourced computation. In said scheme, the verifier requests computation from the prover and verifies the result by checking the output and proof ...
Junghee Lee +4 more
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IEEE Access, 2022 The Blockchain has been given great attention in recent literature among emerging technologies in software architectures. More specifically, when verifiable transactions between untrusted parties are concerned in a safe and reliable environment, its ...
Gaetano Volpe +2 more
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Layered architecture for quantum computing
, 2012 We develop a layered quantum computer architecture, which is a systematic framework for tackling the individual challenges of developing a quantum computer while constructing a cohesive device design.
Alexei Yu. Kitaev +23 more
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Efficient deep CNNs for cross-modal automated computer vision under time and space constraints [PDF]
, 2019 We present an automated computer vision architecture to handle video and image data using the same backbone networks. We show empirical results that lead us to adopt MOBILENETV2 as this backbone architecture.
Amirian, Mohammadreza +4 more
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Interconnection Networks for Scalable Quantum Computers [PDF]
, 2006 We show that the problem of communication in a quantum computer reduces to constructing reliable quantum channels by distributing high-fidelity EPR pairs. We develop analytical models of the latency, bandwidth, error rate and resource utilization of such
Isailovic, Nemanja +3 more
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Simulators for Processors Used in Virtualization: A Survey
IEEE Open Journal of the Computer SocietySimulation imitates the modeled system to the desired level of details in the desired time. Cloud computing shares the resources, and virtualization is the key technology that enables cloud computing.
Swapneel C. Mhatre, Priya Chandran
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Fast Hybrid Data Structure for a Large Alphabet K-Mers Indexing for Whole Genome Alignment
IEEE Access, 2021 The most common index data structures used by whole genome aligners (WGA) are based on suffix trees (ST), suffix arrays, and FM-indexes. These data structures show good performance results as WGA works with sequences of letters over small alphabets; for ...
Rostislav Hrivnak +2 more
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Exchange in silicon-based quantum computer architecture
, 2002 The silicon-based quantum computer proposal has been one of the intensely pursued ideas during the past three years. Here we calculate the donor electron exchange in silicon and germanium, and demonstrate an atomic-scale challenge for quantum computing ...
A. K. Ramdas +11 more
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