Results 51 to 60 of about 1,374,683 (343)

The Caenorhabditis elegans DPF‐3 and human DPP4 have tripeptidyl peptidase activity

FEBS Letters, EarlyView.
The dipeptidyl peptidase IV (DPPIV) family comprises serine proteases classically defined by their ability to remove dipeptides from the N‐termini of substrates, a feature that gave the family its name. Here, we report the discovery of a previously unrecognized tripeptidyl peptidase activity in DPPIV family members from two different species.
Aditya Trivedi, Rajani Kanth Gudipati
wiley   +1 more source

BTCP: Binary Temporal Convolutional Network-Based Data Prefetcher for Low Inference Latency and Storage Overhead

IEEE Access
Data prefetching is crucial for hiding long-latency memory access on modern high-performance processors. Machine learning (ML)-based data prefetchers have demonstrated superior address prediction performance compared with traditional rule-based ...
Chang Ho Ryu, Tae Hee Han
doaj   +1 more source

Crosstalk between the ribosome quality control‐associated E3 ubiquitin ligases LTN1 and RNF10

FEBS Letters, EarlyView.
Loss of the E3 ligase LTN1, the ubiquitin‐like modifier UFM1, or the deubiquitinating enzyme UFSP2 disrupts endoplasmic reticulum–ribosome quality control (ER‐RQC), a pathway that removes stalled ribosomes and faulty proteins. This disruption may trigger a compensatory response to ER‐RQC defects, including increased expression of the E3 ligase RNF10 ...
Yuxi Huang, Satoshi Hashimoto, Sota Ito, Chisato Kikuguchi, Miho Hoshi, Kiyoshi Yamaguchi, Yoichi Furukawa, Toru Suzuki, Toshifumi Inada   +8 more
wiley   +1 more source

Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine

IET Computers & Digital Techniques, 2023
This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency ...
Mark Vousden, Jordan Morris, Graeme McLachlan Bragg, Jonathan Beaumont, Ashur Rafiev, Wayne Luk, David Thomas, Andrew Brown   +7 more
doaj   +1 more source

Identification of Return-Oriented Programming Attacks Using RISC-V Instruction Trace Data

IEEE Access, 2022
An increasing number of embedded systems include dedicated neural hardware. To benefit from this specialized hardware, deep learning techniques to discover malware on embedded systems are needed. This effort evaluated candidate machine learning detection
Daniel F. Koranek, Scott R. Graham, Brett J. Borghetti, Wayne C. Henry   +3 more
doaj   +1 more source

Interplay between circadian and other transcription factors—Implications for cycling transcriptome reprogramming

FEBS Letters, EarlyView.
This perspective highlights emerging insights into how the circadian transcription factor CLOCK:BMAL1 regulates chromatin architecture, cooperates with other transcription factors, and coordinates enhancer dynamics. We propose an updated framework for how circadian transcription factors operate within dynamic and multifactorial chromatin landscapes ...
Xinyu Y. Nie, Jerome S. Menet
wiley   +1 more source

An integrated taxonomy of standard indicators for ranking and selecting supercomputers

IET Computers & Digital Techniques, 2023
Due to the ever‐increasing computing requirements of modern applications, supercomputers are at the centre of attraction as a platform for high‐performance computing.
Davood Maleki, Alireza Mansouri, Ehsan Arianyan   +2 more
doaj   +1 more source

Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance Detection

IEEE Access, 2021
To meet the performance demands of chip multiprocessors, chip designers have increased the capacity and hierarchy of cache memories. Accordingly, a shared lower-level cache reduces conflict misses by adopting a multi-way set-associative structure with ...
Yun-Seok Oh, Eui-Young Chung
doaj   +1 more source

Techniques for improving reliability of computers [PDF]

, 1972
Modular design techniques improve methods of error detection, diagnosis, and recovery. Theoretical computer (MARCS (Modular Architecture for Reliable Computer Systems)) study deals with postulated and modeled technology indigenous to 1975-1980.
Bouricius, W. G., Cater, W. C., Jessep, D. C., Mccarthy, C. E., Milligan, F. G., Wadia, A. B.   +5 more
core   +1 more source

Neural Networks Architecture Evaluation in a Quantum Computer

, 2017
In this work, we propose a quantum algorithm to evaluate neural networks architectures named Quantum Neural Network Architecture Evaluation (QNNAE). The proposed algorithm is based on a quantum associative memory and the learning algorithm for artificial
da Silva, Adenilton José, de Oliveira, Rodolfo Luan F.   +1 more
core   +1 more source