Results 1 to 10 of about 511,028 (202)
Classic McEliece on the ARM Cortex-M4
Transactions on Cryptographic Hardware and Embedded Systems, 2021 This paper presents a constant-time implementation of Classic McEliece for ARM Cortex-M4. Specifically, our target platform is stm32f4-Discovery, a development board on which the amount of SRAM is not even large enough to hold the public key of the ...
Ming-Shing Chen, Tung Chou
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Transactions on Cryptographic Hardware and Embedded Systems, 2021 We present the first Cortex-M4 implementation of the NISTPQC signature finalist Rainbow. We target the Giant Gecko EFM32GG11B which comes with 512 kB of RAM which can easily accommodate the keys of RainbowI.
Tung Chou +2 more
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Design and Implementation of an Atrial Fibrillation Detection Algorithm on the ARM Cortex-M4 Microcontroller [PDF]
Sensors, 2023 At present, a medium-level microcontroller is capable of performing edge computing and can handle the computation of neural network kernel functions.
Marek Żyliński +2 more
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Compact Dilithium Implementations on Cortex-M3 and Cortex-M4
Transactions on Cryptographic Hardware and Embedded Systems, 2020 We present implementations of the lattice-based digital signature scheme Dilithium for ARM Cortex-M3 and ARM Cortex-M4. Dilithium is one of the three signature finalists of the NIST post-quantum cryptography competition.
Denisa O. C. Greconici +2 more
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Optimized implementation of HQC on Cortex-M4
ICT ExpressIn March 2025, NIST selected HQC as a standardized PQC algorithm. Since HQC relies on binary polynomial operations, optimizations for prime-field schemes like Kyber are not directly applicable.
DongCheon Kim +3 more
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Cortex-M4 optimizations for {R,M} LWE schemes
Transactions on Cryptographic Hardware and Embedded Systems, 2020 This paper proposes various optimizations for lattice-based key encapsulation mechanisms (KEM) using the Number Theoretic Transform (NTT) on the popular ARM Cortex-M4 microcontroller.
Erdem Alkim +3 more
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Nibbling MAYO: Optimized Implementations for AVX2 and Cortex-M4
Transactions on Cryptographic Hardware and Embedded SystemsMAYO is a popular high-calorie condiment as well as an auspicious candidate in the ongoing NIST competition for additional post-quantum signature schemes achieving competitive signature and public key sizes.
Ward Beullens +4 more
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Optimizing BIKE for the Intel Haswell and ARM Cortex-M4
Transactions on Cryptographic Hardware and Embedded Systems, 2021 BIKE is a key encapsulation mechanism that entered the third round of the NIST post-quantum cryptography standardization process. This paper presents two constant-time implementations for BIKE, one tailored for the Intel Haswell and one tailored for the ...
Ming-Shing Chen +2 more
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Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4 [PDF]
Transactions on Cryptographic Hardware and Embedded SystemsSQIsign is a well-known post-quantum signature scheme due to its small combined signature and public-key size. However, SQIsign suffers from notably long signing times, and verification times are not short either.
Marius A. Aardal +8 more
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Multi-moduli NTTs for Saber on Cortex-M3 and Cortex-M4
Transactions on Cryptographic Hardware and Embedded Systems, 2021 The U.S. National Institute of Standards and Technology (NIST) has designated ARM microcontrollers as an important benchmarking platform for its Post-Quantum Cryptography standardization process (NISTPQC).
Amin Abdulrahman +5 more
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