Results 261 to 270 of about 135,051 (299)
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International Symposium for Testing and Failure Analysis, 2018
Abstract Gallium Arsenide (GaAs) integrated circuits have become popular these days with superior speed/power products that permit the development of systems that otherwise would have made it impossible or impractical to construct using silicon semiconductors.
Harold Jeffrey M. Consigo +2 more
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Abstract Gallium Arsenide (GaAs) integrated circuits have become popular these days with superior speed/power products that permit the development of systems that otherwise would have made it impossible or impractical to construct using silicon semiconductors.
Harold Jeffrey M. Consigo +2 more
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Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)
Volume 2: Thermal Management; Data Centers and Energy Efficient Electronic Systems, 2013Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC.
Leila Choobineh +3 more
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Journal of Micromechanics and Microengineering, 2020
Among the advanced integrated circuit (IC) integration methods, three-dimensional heterogeneous integration with through-silicon via (TSV) technology showed great potential towards the system-level integration with an increased interconnect density in a smaller footprint. However, the heat mitigation across several dies remains a critical issue in this
Hemanth Kumar Cheemalamarri +3 more
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Among the advanced integrated circuit (IC) integration methods, three-dimensional heterogeneous integration with through-silicon via (TSV) technology showed great potential towards the system-level integration with an increased interconnect density in a smaller footprint. However, the heat mitigation across several dies remains a critical issue in this
Hemanth Kumar Cheemalamarri +3 more
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Deep learning techniques for integrated circuit die performance prediction
MRS Advances, 2022Alexander Kovalenko +2 more
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Metrology, Inspection, and Process Control for Microlithography XXXIII, 2019
Device miniaturization and complication is now stimulating the strong needs for the three dimensional (3D) geometry measurement of the structure. Now in the single-nanometer nodes, the CDs need to be known at multiple pattern heights especially in after-etch inspection. This means SEM measurements is expected to provide 3D contours.
Makoto Suzuki, Ayumi Doi
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Device miniaturization and complication is now stimulating the strong needs for the three dimensional (3D) geometry measurement of the structure. Now in the single-nanometer nodes, the CDs need to be known at multiple pattern heights especially in after-etch inspection. This means SEM measurements is expected to provide 3D contours.
Makoto Suzuki, Ayumi Doi
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Advances in Electronic Packaging, Parts A, B, and C, 2005
This paper presents a method of finite element analysis for calculating moisture concentration in non-isothermal and non-steady states of moisture for integrated circuit packages composed of dissimilar moisture-permeable materials. The method can address non-Fickian behavior of materials in moisture diffusivity.
Hiroyuki Tanaka, Takashi Numata
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This paper presents a method of finite element analysis for calculating moisture concentration in non-isothermal and non-steady states of moisture for integrated circuit packages composed of dissimilar moisture-permeable materials. The method can address non-Fickian behavior of materials in moisture diffusivity.
Hiroyuki Tanaka, Takashi Numata
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Integrated Circuit Die Level Yield Prediction Using Deep Learning
2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2022Petr Lenhard +2 more
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18th International Reliability Physics Symposium, 1980
A technique (the capacitance-ratio test) is described for assessing the water content of hermetic packages containing an integrated circuit die. It is based on a theoretical analysis which shows that the frequency dependence of the capacitance between a selected pair of IC metallisation tracks can be used to derive the moisture induced component of ...
R P Merrett, S P Sim, J P Bryant
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A technique (the capacitance-ratio test) is described for assessing the water content of hermetic packages containing an integrated circuit die. It is based on a theoretical analysis which shows that the frequency dependence of the capacitance between a selected pair of IC metallisation tracks can be used to derive the moisture induced component of ...
R P Merrett, S P Sim, J P Bryant
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IFAC Proceedings Volumes, 1965
Abstract Die standig fortschreitende Entwicklung der verschiedenen Formen integrierter Schaltungen wird einem Evolutionsgedanken unterzuordnen versucht. Ausgehend von dem sich als auserst fruchtbar erweisenden Konzept, die Drucktechnik zur Realisierung elektrischer Schaltungen zu verwenden, wird man systematisch von der kupfer-kaschierten Platine bis
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Abstract Die standig fortschreitende Entwicklung der verschiedenen Formen integrierter Schaltungen wird einem Evolutionsgedanken unterzuordnen versucht. Ausgehend von dem sich als auserst fruchtbar erweisenden Konzept, die Drucktechnik zur Realisierung elektrischer Schaltungen zu verwenden, wird man systematisch von der kupfer-kaschierten Platine bis
openaire +1 more source