Results 261 to 270 of about 366,258 (347)

Gallium Arsenide Integrated Circuits Decapsulation Technique Using Mixed Acid Chemistry For Die-Level Failure Analysis

International Symposium for Testing and Failure Analysis, 2018
Abstract Gallium Arsenide (GaAs) integrated circuits have become popular these days with superior speed/power products that permit the development of systems that otherwise would have made it impossible or impractical to construct using silicon semiconductors.
Harold Jeffrey M. Consigo, Ricardo Calanog, Melissa O. Caseria   +2 more
openalex   +2 more sources

CMOS Sensor Arrays for High Resolution Die Stress Mapping in Packaged Integrated Circuits

IEEE Sensors Journal, 2013
This paper reports the design, calibration and application of multiplexed arrays of piezoresistive field-effect transistor stress sensors fabricated in a standard complementary-metal-oxide semiconductor (CMOS) process. Two complementary arrays of 256-current mirror sensor cells provide high spatial density stress mapping with approximately 300 pts/mm2 ...
Yonggang Chen, R.C. Jaeger, Jeffrey C. Suhling   +2 more
openalex   +2 more sources

Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)

Volume 2: Thermal Management; Data Centers and Energy Efficient Electronic Systems, 2013
Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC.
Leila Choobineh, Nick Vo, Trent Uehling, Ankur Jain   +3 more
openalex   +2 more sources

Determination of temperature distribution in three-dimensional integrated circuits (3D ICs) with unequally-sized die

Applied Thermal Engineering, 2013
Abstract There is much interest in 3D integrated circuits (3D IC) technology for vertical integration of multiple device planes in semiconductor devices. Stacking several device planes vertically offers significant electrical performance improvements. This can also lead to reduced design and manufacturing costs.
Leila Choobineh, Ankur Jain
openalex   +2 more sources

Adhesion Strength at High Temperatures Affected by Moisture for Die-Attach Materials of Integrated Circuit Packages

Advances in Electronic Packaging, Parts A, B, and C, 2005
This paper presents a method of finite element analysis for calculating moisture concentration in non-isothermal and non-steady states of moisture for integrated circuit packages composed of dissimilar moisture-permeable materials. The method can address non-Fickian behavior of materials in moisture diffusivity.
Hiroyuki Tanaka, Takashi Numata
openalex   +2 more sources

3D-SEM challenges: How can we profile in-die 3D geometry of the integrated circuits? (Conference Presentation)

Metrology, Inspection, and Process Control for Microlithography XXXIII, 2019
Device miniaturization and complication is now stimulating the strong needs for the three dimensional (3D) geometry measurement of the structure. Now in the single-nanometer nodes, the CDs need to be known at multiple pattern heights especially in after-etch inspection. This means SEM measurements is expected to provide 3D contours.
Makoto Suzuki, Ayumi Doi
openalex   +2 more sources

Some of the next articles are maybe not open access.

Related searches:

A Miniaturized Ka-Band Bandpass Filter Using Folded Hybrid Resonators Based on Monolithic Microwave Integrated Circuit Technology

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2021
A miniaturized Ka-band bandpass filter (BPF) is presented by using monolithic microwave integrated circuit (MMIC) technology in this brief. Aiming at low cost and high integration, small die area of MMIC BPFs is significantly required for RF front-end ...
Guangxu Shen, W. Che, W. Feng, Yongrong Shi, Yiming Shen, Feng Xu   +5 more
semanticscholar   +1 more source

Novel technology of III-V die-bonded SOI photonic integrated circuits

Emerging Applications in Silicon Photonics II, 2021
In the frame of the H2020 PICTURE project, we designed and developed densely integrated photonic devices and transceiver (TRx) circuits for high bit-rate telecom and datacom applications. We implemented a process with four different InP-based dies bonded on SOI wafers.
Delphine Néel, Alexandre Shen, Pierre Fanneau de La Horie, Nicolas I. Vaissière, Arnaud Wilk, Viviane Muffato, Stéphane Malhouitre, Valentin Ramez, Yohan Desières, Karim Hassan   +9 more
openaire   +1 more source

1.6 Tbps Silicon Photonics Integrated Circuit and 800 Gbps Photonic Engine for Switch Co-Packaging Demonstration

Journal of Lightwave Technology, 2020
We describe the performance of high bandwidth-density silicon photonic based integrated circuits (SiPh ICs) that enable the first fully functional photonic engine (PE) module co-packaged with an Ethernet switch.
S. Fathololoumi, D. Hui, Susheel Jadhav, Jian Chen, K. Nguyen, M. N. Sakib, Z. Li, Hari Mahalingam, Siamak Amiralizadeh, Nelson N. Tang, Harinadh Potluri, M. Montazeri, Harel Frish, R. Defrees, Christopher Seibert, A. Krichevsky, J. Doylend, J. Heck, R. Venables, A. Dahal, A. Awujoola, A. Vardapetyan, Guneet Kaur, M. Cen, Vishnu Kulkarni, Syed S. Islam, R. L. Spreitzer, S. Garag, A. Alduino, Rk Chiou, L. Kamyab, S. Gupta, B. Xie, R. S. Appleton, S. Hollingsworth, S. McCargar, Y. Akulova, K. M. Brown, R. Jones, Daniel Zhu, T. Liljeberg, L. Liao   +41 more
semanticscholar   +1 more source

Inter-die signaling in three dimensional integrated circuits

2008 IEEE Custom Integrated Circuits Conference, 2008
This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18 mum MIT Lincoln Laboratories 3D FDSOI 1.5 V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 mm2 per tier was designed and tested.
Christopher Mineo, Ravi Jenkal, Samson Melamed, W. Rhett Davis   +3 more
openaire   +1 more source