Machine Learning Integrated Pseudo-3-D Flow for Monolithic 3-D ICs
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2021 Monolithic 3-D (M3-D) IC design is a manufacturing technique that opens several new possibilities of chip design and exploration for power, performance, area (PPA), and cost benefits.
Sai Pentapati, Bon Woong Ku, Sungkyu Lim
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VLSI Reliability in Europe [PDF]
, 1993 Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described.
Verweij, J.F., Verweij, Jan F.
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BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits [PDF]
2007 Design, Automation & Test in Europe Conference & Exhibition, 2007 Peer ...
Zjajo, Amir +2 more
openaire +3 more sources
Characterization of an embedded RF-MEMS switch [PDF]
, 2010 An RF-MEMS capacitive switch for mm-wave integrated circuits, embedded in the BEOL of 0.25μm BiCMOS process, has been characterized. First, a mechanical model based on Finite-Element-Method (FEM) was developed by taking the residual stress of the thin ...
Ehwald, K. E. +10 more
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A heuristic fault based optimization approach to reduce test vectors count in VLSI testing
Journal of King Saud University: Computer and Information Sciences, 2019 In this work we have proposed a heuristic approach to reduce the test vector count during VLSI testing of standard ISCAS circuits. With the shrinking die-space and increasing circuitry on a single Integrated circuit, the number of test vectors required ...
Vinod Kumar Khera +2 more
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On Timing Model Extraction and Hierarchical Statistical Timing Analysis [PDF]
, 2013 In this paper, we investigate the challenges to apply Statistical Static Timing Analysis (SSTA) in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and
Li, Bing +3 more
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A 216–256 GHz fully differential frequency multiplier-by-8 chain with 0 dBm output power [PDF]
, 2018 Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence
Borngräber, Johannes +6 more
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An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors
Sensors, 2021 The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle
Folla Kamdem Jérôme +6 more
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Embedded 5V-to-3.3V Voltage Regulator for Supplying Digital ICs in 3.3V CMOS Technology [PDF]
, 1998 A fully integrated 5 V-to-3.3 V supply voltage regulator for application in digital IC's has been designed in a 3.3 V 0.5 μm CMOS process. The regulator is able to deliver peak current transients of 300 mA, while the output voltage remains within a ...
Besten, Gerrit W. den, Nauta, Bram
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Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF
IEEE Access, 2022 This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor.
Alina-Teodora Grajdeanu +5 more
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