Results 91 to 100 of about 13,935 (298)
This paper proposes a highly efficient ferroelectric artificial synapse device based on an oxide semiconductor and SnCl2‐inserted P(VDF‐TrFE) gate dielectric layer. This FeFET significantly improved the synaptic performance due to the ion‐dipole interaction.
Hyun‐Soo Kim +14 more
wiley +1 more source
A Physical Model for the Hysteresis in MoS2 Transistors
Even though the hysteresis in the gate transfer characteristics of two-dimensional (2D) transistors is a frequently encountered phenomenon, the physics behind it are up to now only barely understood, let alone modeled.
Theresia Knobloch +8 more
doaj +1 more source
Ultrawide Bandwidth Optomechanical Magnetometry Using Flux Concentration
High‐permeability flux concentrators enable ultrawide‐bandwidth chip‐scale optomechanical magnetometry by exploiting magnetic nonlinearity to up‐convert low‐frequency fields to the mechanical resonance, where sensitivity is optimal. This enables flat wideband operation over more than four orders of magnitude, from tens of kilohertz to sub‐hertz ...
Benjamin J. Carey +6 more
wiley +1 more source
Electroforming‐free TiN/SiOx/Cu/SiOx/TiN memristive devices exploit pancake‐like Cu nanoparticles embedded in a SiOx double layer to create a heterogeneous Schottky‐barrier landscape. Under bias, oxygen‐vacancy redistribution progressively lowers local barriers and recruits initially inactive Cu‐PC pathways into a parallel conduction ensemble, enabling
Rouven Lamprecht +10 more
wiley +1 more source
Suppression of hysteresis in ultrathin tellurium transistors
Tellurium (Te) is a promising p-type semiconductor but suffers from pronounced electrical hysteresis that limits device stability. The origin of hysteresis in Te field-effect transistors is investigated, and effective suppression strategies are ...
Sung-Tsun Wang +16 more
doaj +1 more source
Hysteresis Dynamics in Double-Gated n-Type WSe2 FETs With High-k Top Gate Dielectric
We propose double-gated n-type WSe2 FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO2 ALD on an Al2O3 seed layer obtained from the evaporation and oxidation by air exposure of a 1.5
Nicolo Oliva +6 more
doaj +1 more source
Monolithic UV‐ozone oxidation of Ta forms an ultrathin Ta2O5/TaOx bilayer enabling resistive switching with a vertical defect gradient. A stoichiometric surface layer over an oxygen‐deficient sublayer promotes localized filament nucleation near the top interface, enabling low‐voltage operation, and reduced cycle‐to‐cycle variability.
Seunghoon Yang +11 more
wiley +1 more source
A generalizable strategy for fabricating regular porous, chemically intact conjugated polymer channels reveals how porosity benefits organic electrochemical transistors. Composition‐dependent performance enhancement is linked to charge carrier mobility, volumetric capacitance, and effective doped volume.
Geon Gug Yang +4 more
wiley +1 more source
Dielectric electro-active polymer (DEAP) materials, also called artificial muscle, are a kind of EAP smart materials with extraordinary strains up to 30% at a high driving voltage.
Mengmeng Li +3 more
doaj +1 more source
Giant Electrostriction in Halide Perovskites Revisited With Double‐Modulation Interferometry
A giant electrostrictive effect in lead halide perovskites had been reported previously. This work uses sensitive interferometry to measure the electromechanical response of various halide perovskite samples. The results reveal no intrinsic electrostrictive compression. Instead, the materials expand primarily under an applied electric field as a result
Philipp Ramming +4 more
wiley +1 more source

