Results 131 to 140 of about 4,746 (161)

A high lock-in speed digital phase-locked loop

IEEE Transactions on Communications, 1991
A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z-transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model.
Shi Hao, Yan Puqiang
openaire   +1 more source

Modeling and Simulation of Digital Phase-Locked Loop in Simulink

2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2018
This paper presents a high-level model for a digital phase-locked loop implemented in Simulink. This modeling enables the flexible and fast estimation of the design behavior and parameters before transistor-level implementation. The design includes a digital controlled oscillator that is defined using a linear s-domain model. Furthermore, the design of
Parkalian, N., Robens, M., Grewinz, C., Christ, V., Liebau, D., Muralidharan, P., Nielinaer, D., Yegin, U., Zambanini, A., van Waasen, Stefan   +9 more
openaire   +1 more source

Digital Phase Lock Loops

2006
Saleh R. Al-araji, Zahir M. Hussain, Mahmoud A. Al-qutayri   +2 more
  +5 more sources

NONLINEAR DYNAMICS OF DIGITAL PHASE-LOCKED LOOPS WITH DELAY

International Journal of Bifurcation and Chaos, 1994
We investigate numerically and analytically the nonlinear dynamics of a system consisting of two self-synchronizing pulse-coupled nonlinear oscillators with delay. The particular system considered consists of connected digital phase-locked loops. We find mapping equations that govern the system and determine the synchronization properties.
de Sousa Vieira, Maria, Lichtenberg, Allan J., Lieberman, Michael A.   +2 more
openaire   +1 more source

On Optimum Digital Phase-Locked Loops

IEEE Transactions on Communications, 1968
This paper gives the design procedure of optimum digital filters for analog-digital phase-locked loops. The inputs considered are the step and ramp change in phase. The digital filters can easily be realized on the digital computer or otherwise. Design curves are given to choose proper noise bandwidth, sampling period, and loop parameters.
openaire   +1 more source

Simulation of digital phase locked loops

2021
68
openaire   +1 more source

All Digital Phase-Locked Loops

1998
In this chapter, we are going to extend our survey to loops that have do not have analog prototypes. Lindsey and Chie [1] performed a 1981 survey of digital PLLs that is recommended to the reader desiring additional architectures.
openaire   +1 more source

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

IEEE Transactions on Circuits and Systems Part 2: Express Briefs, 2007
Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram   +2 more
exaly  

Novel quick-response, digital phase-locked loop

Electronics Letters, 1988
S Chattopadhyay
exaly  

A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector

IEEE Journal of Solid-State Circuits, 2018
Taekwang Jang, Seokhyeon Jeong, Dongsuk Jeon   +2 more
exaly