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Quantization Effects in All-Digital Phase-Locked Loops
IEEE Transactions on Circuits and Systems II: Express Briefs, 2007This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band phase noise is not only caused by the phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO ...
P. Madoglio +4 more
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A survey of digital phase-locked loops
Proceedings of the IEEE, 1981The purpose of this paper is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980. The DPLL represents the heart of the Building blocks required in the implementation of coherent (all digital) communications and tracking receivers.
W.C. Lindsey, null Chak Ming Chie
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A digital phase‐locked loop with and filter
Electronics and Communications in Japan (Part I: Communications), 1980AbstractIn general, it is known that if the stationary characteristics of a PPL, phase‐locked loop, are improved, its transient response characteristics are deteriorated, while if the transient response characteristics are improved, its stationary characteristics are deteriorated.
Taiichiro Kurita +3 more
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Fractional-Order Digital Phase-Locked Loop
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007A fractional-order digital phase-locked loop (FODPLL) is proposed. The FODPLL model is developed by approximating a fractional-order digital controlled-oscillator (FODCO) with a finite dimensional discrete transfer function. The design of FODPLLs model is simplified where one only needs to design a FODCO.
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Comparison and Simulation of Analog and Digital Phase Locked Loop
2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2018This paper presents a comparative study between the two basic types of Phase locked loop (PLL) i.e. Analog phase locked loop (APLL) and Digital Phase locked loop (DPLL) and their implementation in Simulink. It has been observed that different types of PLL have different performance parameters and response time.
Abhishek Godave +2 more
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STABILITY OF SYNCHRONIZATION IN NETWORKS OF DIGITAL PHASE-LOCKED LOOPS
International Journal of Bifurcation and Chaos, 1995We analyze the linear stability of the synchronized state in networks of N identical digital phase-locked loops. These are pulse-coupled oscillator arrays in which the frequency (rather than the phase) of each oscillator is updated discontinuously whenever that oscillator reaches a specific phase in its cycle.
Goldsztein, Guillermo +1 more
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Quantizing and Sampling Considerations in Digital Phased-Locked Loops
IEEE Transactions on Communications, 1974Quantization and sampling effects on the digital phasedlocked loop (DPLL) structures obtained for demodulation of anglemodulated signals using extended Kalman filter algorithms are investigated for the high signal-to-noise ratio (SNR) case in this paper. First, the problem of quantization is considered.
Gorman Thomas Hurst, Someshwar C. Gupta
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Unbiased Finite-Memory Digital Phase-Locked Loop
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the ...
Sung Hyun You +4 more
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On the Performance of Digital Phase Locked Loops in the Threshold Region
IEEE Transactions on Communications, 1974Extended Kalman filter algorithms are used to obtain a digital phase lock loop structure for demodulation of angle modulated signals. It is shown that the error variance equations obtained directly from this structure enable one to predict threshold if one retains higher frequency terms.
G. T. Hurst, S. C. Gupta
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A New Approach on Design of a Digital Phase-Locked Loop
IEEE Signal Processing Letters, 2016In this letter, we propose a new approach to the design of a digital phase-locked loop (DPLL) with a finite impulse response (FIR) structure, deadbeat property, and $H_\infty$ performance. This DPLL is called the deadbeat $H_\infty$ FIR DPLL (DHFDPLL).
Choon Ki Ahn +2 more
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