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A digital loop filter for a Phase Locked Loop
2011 17th International Conference on Digital Signal Processing (DSP), 2011Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs.
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Response of an All Digital Phase-Locked Loop
IEEE Transactions on Communications, 1974An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of ...
Joseph Garodnick +2 more
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BIST for phase-locked loops in digital applications
International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 2003Phase-locked loops (PLLs) are an essential building block of most digital and mixed-signal ICs. This paper describes a built-in self-test (BIST) circuit that tests the key analog parameters of PLLs, using only logic gates that can be synthesized from a hardware description language (HDL). The parameters tested include lock range, lock time, RMS jitter,
Stephen K. Sunter, Aubin Roy
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Advanced digital phase-locked loops
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013Analog PLLs do not scale down as process and are not amenable to noise-cancellation and other calibration algorithms; Digital PLLs exploit CMOS scaling and allow for simple, accurate implementation of digiphase and two-point modulation; Typically, DPLLs require TDCs with tight resolution to achieve low phase noise and fractional-spur level, which ...
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IETE Journal of Education, 2011
AbstractThe paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed.
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AbstractThe paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed.
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2015
One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated ...
Basab Bijoy Purkayastha +1 more
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One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated ...
Basab Bijoy Purkayastha +1 more
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Quasi-Optimum Digital Phase-Locked Loops
IEEE Transactions on Communications, 1973Quasi-optimum digital phase-locked loops (DPLL) are derived utilizing nonlinear estimation theory. Nonlinear approximations are employed to yield realizable loop structures. Baseband equivalent loop gains are derived, which, under high signal-to-noise ratio conditions may be calculated off line.
Darryl R. Polk, Someshwar C. Gupta
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2022
This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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A Fast-Locking Digital Phase-Locked Loop
Third International Conference on Information Technology: New Generations (ITNG'06), 2006A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results ...
Mahmoud Fawzy Wagdy, Srishti Vaishnava
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Nonlinear dynamics of a digital phase locked loop
IEEE Transactions on Communications, 1989A second-order digital phase-locked loop may exhibit unusual behavior for some parameters due to a fractal boundary between the basin of attraction of the locked fixed point and the attracting basins of coexisting periodic orbits. The usual optimization criterion of the loop parameters using linearized analysis is insufficient, due to coexisting ...
Greg M. Bernstein +2 more
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