Results 11 to 20 of about 1,070 (143)

A 5.5–7.5‐GHz band‐configurable wake‐up receiver fully integrated in 45‐nm RF‐SOI CMOS

IET Circuits, Devices and Systems, 2022
This work investigates a 5.5–7.5‐GHz band‐configurable duty‐cycled wake‐up receiver (WuRX) fully implemented in a 45‐nm radio‐frequency (RF) silicon‐on‐insulator (SOI) complementary‐metal‐oxide‐semiconductor (CMOS) technology.
Rui Ma, Florian Protze, Frank Ellinger
doaj   +2 more sources

Time-Domain ADPLL BPSK, QPSK, and 8PSK Demodulators

Journal of Electrical and Computer Engineering
Time-domain all-digital-phase-locked-loop phase-shift-keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low-voltage nanoscale CMOS techology.
Phanumas Khumsat, Thanabodee Koyphol, Tan Thongruk, Tidarat Inyod   +3 more
doaj   +2 more sources

A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique

IET Circuits, Devices &Systems, Volume 17, Issue 1, Page 13-28, January 2023., 2023
A dual‐path signal‐superposition technique that can address issues which pose challenges in the designs of high speed I/Os with low electro‐magnetic interference/radiations (EMI/EMR) applications is proposed. This work demonstrates an output slew rate lower than 1 V/ns at data rate of hundreds of Mbps or above over PVT, without using huge on‐board ...
Xiaoyan Gui, Renjie Tang, Kai Li, Kanan Wang, Dan Li, Quan Pan, Li Geng   +6 more
wiley   +1 more source

A system‐level performance evaluation of a reconfigurable filtenna in the presence of in‐ and out‐of‐band blockers

IET Communications, Volume 16, Issue 20, Page 2492-2500, December 2022., 2022
Abstract Direct RF sampling has been suggested as a solution for receivers that are flexible in frequency and across standards, while utilising only a single radio frequency front‐end. However there are concerns about their robustness in the presence of out‐of‐band and in‐band blockers.
Stephen Henthorn, Kenneth Lee Ford, Timothy O'Farrell   +2 more
wiley   +1 more source

An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking

IEEE Access, 2021
This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman, Arash Hejazi, Imran Ali, Muhammad Asif, Seongjin Oh, Pervesh Kumar, Younggun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo, Kang-Yoon Lee   +14 more
doaj   +1 more source

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

IEEE Access, 2022
An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented.
Junghoon Jin, Seungjun Kim, Jongsun Kim
doaj   +1 more source

A fractional‐N MASH2‐k FDC phase‐locked loop architecture enabling higher‐order quantisation noise shaping

Electronics Letters, Volume 58, Issue 7, Page 274-276, March 2022., 2022
Abstract The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability. A MASH2‐k FDC PLL architecture enabling (k + 2)th‐order noise shaping for more flexible loop design optimization and for a wider loop bandwidth to suppress the noise from the digitally ...
Ryoga Iwashita, Zule Xu, Masaru Osada, Tetsuya Iizuka   +3 more
wiley   +1 more source

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

IEEE Access, 2021
This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output
Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim   +6 more
doaj   +1 more source

Low‐power multi‐band injection‐locked wireless receiver in 0.13 μm CMOS

IET Circuits, Devices &Systems, Volume 15, Issue 6, Page 522-539, September 2021., 2021
Abstract The design and analysis of a low‐power multi‐band injection‐locked wireless receiver, implemented in complementary metal–oxide–semiconductor (CMOS) 130 nm technology, for wireless sensor network (WSN) applications are presented. The proposed receiver composed of an injection‐locked oscillator (ILO), low‐noise amplifier (LNA), and an envelope ...
Jared Mercier, Yushi Zhou
wiley   +1 more source

A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control

Electronics Letters, Volume 57, Issue 5, Page 209-211, March 2021., 2021
Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun, Yushi Zhou, Zhanjun Bai, Yong Chen   +3 more
wiley   +1 more source