Results 191 to 200 of about 18,499 (235)

Optimizing the DRAM refresh count for merged DRAM/logic LSIs

Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98, 1998
In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. Frequent refreshes increase power consumption. Also, they disturb normal DRAM accesses leading to performance degradation. In order to overcome this problem, we propose several DRAM refresh architectures.
Taku Ohsawa, Koji Kai, Kazuaki J. Murakami   +2 more
openaire   +1 more source

Heterogeneous memory management for 3D-DRAM and external DRAM with QoS

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013
This paper presents an innovative memory management approach to utilize both 3D-DRAM and external DRAM (ex-DRAM). Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM ...
Le-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Houman Homayoun   +3 more
openaire   +1 more source

VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 2018
A DRAM chip requires periodic refresh operations to prevent data loss due to charge leakage in DRAM cells. Refresh operations incur significant performance overhead as a DRAM bank/rank becomes unavailable to service access requests while being refreshed.
Anup Das, Hasan Hassan, Onur Mutlu
openaire   +1 more source

A tribute to graphics DRAMs

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing, 2003
High speed graphics subsystems used some of the earliest application specific DRAMs. Knowledge gained from working with these specialized parts has provided a background for many of the innovations seen today in high speed DRAMs, fast core DRAMs, and high bandwidth embedded DRAMs.
openaire   +1 more source

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads

IEEE International Symposium on High-Performance Comp Architecture, 2012
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However, writes must be eventually processed and they often delay pending reads.
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi   +4 more
openaire   +1 more source

A customized design of DRAM controller for on-chip 3D DRAM stacking

IEEE Custom Integrated Circuits Conference 2010, 2010
To address the “memory wall” challenge, on-chip memory stacking has been proposed as a promising solution. The stacking memory adopts three-dimensional (3D) IC technology, which leverages through-silicon-vias (TSVs) to connect layers, to dramatically reduce the access latency and improve the bandwidth without the constraint of I/O pins.
Tao Zhang 0032, Kui Wang, Yi Feng 0003, Xiaodi Song, Lian Duan, Yuan Xie 0001, Xu Cheng 0001, Youn-Long Lin   +7 more
openaire   +1 more source

PIPF-DRAM

Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022
Nezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad   +2 more
openaire   +1 more source

Physical limits of VLSI DRAMs

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1984
This paper describes the physical limits of VLSI dynamic random-access memories (dRAM's). To achieve memory capacities in the multimegabit range, the significant limits inherent in conventional dRAM technology must be identified and overcome. Limits associated with cell components may be circumvented using an approach that treats the dRAM as a ...
L.L. Lewyn, J.D. Meindl
openaire   +1 more source

Fine-grained DRAM

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Future GPUs and other high-performance throughput processors will require multiple TB/s of bandwidth to DRAM. Satisfying this bandwidth demand within an acceptable energy budget is a challenge in these extreme bandwidth memory systems. We propose a new high-bandwidth DRAM architecture, Fine-Grained DRAM (FGDRAM), which improves bandwidth by 4× and ...
Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson 0002, Aditya Agrawal, Stephen W. Keckler, William J. Dally   +6 more
openaire   +1 more source

DRAM: Efficient adaptive MCMC

Statistics and Computing, 2006
We propose to combine two quite powerful ideas that have recently appeared in the Markov chain Monte Carlo literature: adaptive Metropolis samplers and delayed rejection. The ergodicity of the resulting non-Markovian sampler is proved, and the efficiency of the combination is demonstrated with various examples.
H. HAARIO, M. LAINE, MIRA, ANTONIETTA, E. SAKSMAN   +3 more
openaire   +3 more sources