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Session 23 overview: DRAM, MRAM & DRAM interfaces

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017
Dynamic memories are at the heart of every computing system. Improvements in the memory sub-system are therefore directly impacting user experience - battery-powered systems operate longer, graphics are crisper and our phones will simply react more smoothly.
Takefumi Yoshikawa, Seung-Jun Bae, Leland Chang   +2 more
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Physical limits of VLSI DRAMs

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1984
This paper describes the physical limits of VLSI dynamic random-access memories (dRAM's). To achieve memory capacities in the multimegabit range, the significant limits inherent in conventional dRAM technology must be identified and overcome. Limits associated with cell components may be circumvented using an approach that treats the dRAM as a ...
L.L. Lewyn, J.D. Meindl
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Which DRAM will win the great DRAM sweepstakes?

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1993
A summary of recent DRAM (dynamic random-access memory) development is presented. DRAM architectures using different philosophies have recently emerged to fill the needs of high-performance systems. Among these are cached DRAMs (CDRAMs), Rambus DRAMs (RDRAMs), RamLink DRAMs, and synchronous DRAMs (SDRAMs).
M. Slater, M. Farmwald, M. Hannah, D.V. James, J.A. Karp, M. Kumanoya, J. Szarek   +6 more
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Transparent-refresh DRAM (TReD) using dual-port DRAM cell

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 2003
A novel memory circuit, the transparent-refresh DRAM (TReD), is proposed to make a dynamic random-access memory (DRAM) virtually refresh-free, and a test device is successfully fabricated. The TReD uses dual-port dynamic RAM cells, one port of which is assigned for a refresh operation and the other port is assigned for a normal read/write operation ...
T. Sakurai, K. Nogami, K. Sawada, T. Iizuka   +3 more
openaire   +1 more source

PRET DRAM controller

Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2011
Hard real-time embedded systems employ high-capacity memories such as Dynamic RAMs (DRAMs) to cope with increasing data and code sizes of modern designs. However, memory controller design has so far largely focused on improving average-case performance.
Jan Reineke, Isaac Liu, Hiren D. Patel, Sungjun Kim, Edward A. Lee   +4 more
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PIPF-DRAM

Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022
Nezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad   +2 more
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DRAMS scheme

BMJ, 1991
R. Earwicker, T. Wolff
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True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

Advanced Materials, 2023
Yanqing Wu
exaly  

DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks

2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2022
Stijn Eyerman, Wim Heirman, Ibrahim Hur
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Drams to grams

Physics Bulletin, 1974
Some 20 years ago I was asked how many grams made a dram. Knowing the figure to be approximately 1.77 and knowing the value of √3 be 1.732 I facetiously said: 'Call it √π, it will be near enough!'
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