Results 41 to 50 of about 97,626 (219)
HMB in DRAM-less NVMe SSDs: Their usage and effects on performance.
PLoS ONE, 2020 Solid-state drives (SSDs) that do not have internal dynamic random-access memory (DRAM) are being widely spread for client SSD and embedded SSD markets in recent years because they are cheap and consume less power.
Kyusik Kim, Taeseok Kim
doaj +1 more source
Making DRAM Refresh Predictable [PDF]
2010 22nd Euromicro Conference on Real-Time Systems, 2010 Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory can assure deadlines for a given task set when periods and worst-case execution times (WCETs) of tasks are known.
Balasubramanya Bhat, Frank Mueller
openaire +1 more source
Atomic Layer Deposition in Transistors and Monolithic 3D Integration
Advanced Functional Materials, EarlyView.Transistors are fundamental building blocks of modern electronics. This review summarizes recent progress in atomic layer deposition (ALD) for the synthesis of two‐dimensional (2D) metal oxides and transition‐metal dichalcogenides (TMDCs), with particular emphasis on their enabling role in monolithic three‐dimensional (M3D) integration for next ...
Yue Liu +5 more
wiley +1 more source
A Survey of Hybrid Main Memory Architectures
Sakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi, 2019 Rapidly evolving technology, increased internet speedand capacity, and the widespread use of mobile technologies have increased thedemands for faster applications and less power consumption of modern electronicsystems.
Ahmet Sertbaş +3 more
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Adaptive-latency DRAM: Optimizing DRAM timing for the common-case [PDF]
2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015 In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios.
Donghyuk Lee +6 more
openaire +1 more source
RowHammer: Reliability Analysis and Security Implications [PDF]
, 2016 As process technology scales down to smaller dimensions, DRAM chips become more vulnerable to disturbance, a phenomenon in which different DRAM cells interfere with each other's operation. For the first time in academic literature, our ISCA paper exposes
Daly, Ross +8 more
core
AI‐Optimized Vanadium Oxide Multilayers for More Than 20‐fold Enhancement in Bolometric Performance
Advanced Science, EarlyView.Machine‐learning‐optimized WxV1‐xOy multilayer thin films with graded doping achieve a high TCR (7.3 % K−1), reduced hysteresis, and low noise under CMOS‐compatible growth conditions. This approach overcomes the long‐standing trade‐off in microbolometers between linear response and performance, offering a universal bolometric parameter greatly enhanced
Jin‐Hyun Choi +8 more
wiley +1 more source
In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs
Micromachines, 2019 Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations.
Ho Hyun Shin, Eui-Young Chung
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DRAM triggers lysosomal membrane permeabilization and cell death in CD4(+) T cells infected with HIV. [PDF]
PLoS Pathogens, 2013 Productive HIV infection of CD4(+) T cells leads to a caspase-independent cell death pathway associated with lysosomal membrane permeabilization (LMP) and cathepsin release, resulting in mitochondrial outer membrane permeabilization (MOMP).
Mireille Laforge +9 more
doaj +1 more source
Advanced Science, EarlyView.The HfxZr1‐xO2‐based ferroelectric/antiferroelectric bilayer capacitor exhibits morphotropic‐phase‐boundary behavior with a high dielectric constant (∼52) at 2 V. Phase engineering stabilizes o/t‐phase coexistence and suppresses m‐phase formation, enabling capacitance enhancement and self‐optimization under cycling for scalable low‐voltage, high‐κ ...
Junseok Kim +5 more
wiley +1 more source