Results 41 to 50 of about 106,345 (262)
Novel STI Technology for Enhancing Reliability of High-k/Metal Gate DRAM
IEEE AccessThe challenges associated with semiconductor are increasing because of the rapid changes in the semiconductor market and the extreme scaling of semiconductors, with some processes reaching their technological limits.
Hyojin Park +5 more
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Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage
Micromachines, 2021 With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage ...
Kyung Min Koo +4 more
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Making DRAM Refresh Predictable [PDF]
2010 22nd Euromicro Conference on Real-Time Systems, 2010 Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory can assure deadlines for a given task set when periods and worst-case execution times (WCETs) of tasks are known.
Balasubramanya Bhat, Frank Mueller
openaire +1 more source
Does a Morphotropic Phase Boundary Exist in ZrxHf1‐xO2‐Based Thin Films?
Advanced Functional Materials, EarlyView.This study investigates 6 nm zirconium‐rich hafnium‐zirconium oxide thin–film metal–insulator–metal capacitors using a combination of experimental methods and machine learning–based molecular dynamics simulations to provide insight into the physical mechanisms that enhance the dielectric constant near 0 V and attribute it to the field‐induced ...
Pramoda Vishnumurthy +9 more
wiley +1 more source
HMB in DRAM-less NVMe SSDs: Their usage and effects on performance.
PLoS ONE, 2020 Solid-state drives (SSDs) that do not have internal dynamic random-access memory (DRAM) are being widely spread for client SSD and embedded SSD markets in recent years because they are cheap and consume less power.
Kyusik Kim, Taeseok Kim
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RowHammer: Reliability Analysis and Security Implications [PDF]
, 2016 As process technology scales down to smaller dimensions, DRAM chips become more vulnerable to disturbance, a phenomenon in which different DRAM cells interfere with each other's operation. For the first time in academic literature, our ISCA paper exposes
Daly, Ross +8 more
core
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case [PDF]
2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015 In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios.
Donghyuk Lee +6 more
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Advanced Materials, EarlyView.Super‐steep subthreshold swing (SS) below 60 mV dec−1 is demonstrated in graphene/IGZO cold source transistor arrays. Linear density of states with Dirac cone in graphene suppressed the Boltzmann thermal tail, while high‐k HfO2 dielectric having small body factor enhanced gating efficiency, hereby further reducing SS. An average SS of ≈46.4 mV dec−1 is
Seyoung Oh +13 more
wiley +1 more source
In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs
Micromachines, 2019 Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations.
Ho Hyun Shin, Eui-Young Chung
doaj +1 more source
OS Scheduling Algorithms for Memory Intensive Workloads in Multi-socket Multi-core servers
, 2018 Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are routinely used for running various server applications.
Durbhakula, Murthy
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