Results 251 to 260 of about 135,198 (280)

A Reconfiguration Manager for Dynamically Reconfigurable Hardware

IEEE Design and Test of Computers, 2005
Dynamic reconfiguration has been a technology solution in search of the right problem to solve. Effective use of the technology requires new programming and task management models. This article describes an approach to dynamic reconfiguration that reduces reconfiguration latency to the point where dynamic multimedia applications can now exploit such ...
J. Resano, D. Mozos, D. Verkest, F. Catthoor   +3 more
openaire   +1 more source

Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures

Circuits, Systems, and Signal Processing, 2017
Dynamically reconfigurable architectures, such as NATURE, achieve high logic density and low reconfiguration latency compared to traditional field-programmable gate arrays. Unlike fine-grained NATURE, reconfigurable DSP block incorporated NATURE architecture achieves significant improvement in performance for mapping compute-intensive arithmetic ...
Warrier, Rakesh, Zhang, Wei, Vun, Chan Hua   +2 more
openaire   +2 more sources

Dynamically reconfigurable protocol transducer

2006 IEEE International Conference on Field Programmable Technology, 2006
Protocol transducer synthesis is one of the most significant issues for efficient IP core reuse in SoC design. The authors proposed automatic protocol transducer synthesis method (Watanabe et al., 2006), (Ishikawa et al., 2006). In this paper, an application of the protocol synthesis method to reconfigurable architecture on FPGA was proposed that ...
Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita   +4 more
openaire   +1 more source

Dynamically reconfigurable VLD circuit

2009 IEEE 13th International Symposium on Consumer Electronics, 2009
A dynamically reconfigurable VLD (variable length decode) circuit is proposed. In this circuit, several comparators decode at input bitstream in parallel. Furthermore it can also decode next code in same time, using some comparators. The rate of number of comparators used for parallel and next code decoding is variable and the reconfiguration can be ...
Kiyotaka Komoku, null Takashi Miyake, null Takayuki Morishita, null Nobuo Sasaki   +3 more
openaire   +1 more source

Dynamically Reconfigurable Cores

2001
Dynamic reconfiguration of digital circuits on FPGAs has been an area of active research for the past decade. The identification of generic classes of circuits that would benefit from being dynamically reconfigured remains a key, open problem. We report on an investigation of the application of dynamic reconfiguration to programmable, multi-function ...
John MacBeth, Patrick Lysaght
openaire   +1 more source

Dynamically reconfigurable microphone arrays

2011 IEEE International Conference on Robotics and Automation, 2011
Robotic sound localization has traditionally been restricted to either on-robot microphone arrays or embedded microphones in aware environments, each of which have limitations due to their static configurations. This work overcomes the static configuration problems by using visual localization to track multiple wireless microphones in the environment ...
E. Martinson, B. Fransen
openaire   +1 more source

Control of Dynamic Reconfiguration

2009
This Chapter describes the mechanisms used to control the dynamic reconfiguration aspects of the MORPEUS system. The base is formed by real-time operating system and is topped by a allocation and scheduling system for reconfigurable operations.
Thoma, F., Becker, J.
openaire   +1 more source

Dynamically reconfiguring multimedia components

Proceedings of the 8th ACM SIGOPS European workshop on Support for composing distributed applications, 1998
Distributed multimedia systems are potentially subject to frequent and ongoing evolution of application structures. In such systems it is often unacceptable for reconfigurations to fail or to only partially succeed. This paper describes the reconfiguration architecture of the DJINN multimedia programming framework.
Scott Mitchell, Hani Naguib, George Coulouris, Tim Kindberg   +3 more
openaire   +1 more source

MVS Dynamic Reconfiguration Management

IBM Journal of Research and Development, 1992
This paper presents an overview of the Dynamic Reconfiguration Management (DRM) function of MVS/ESA™ and its support of the IBM Enterprise System/9000™ family of machines. Dynamic Reconfiguration Management is the ability to select a new I/O configuration definition without needing to perform a power-on reset (POR) of the hardware or an initial program
R. Cwiakala, J. D. Haggar, H. M. Yudenfriend   +2 more
openaire   +1 more source

Reconfigurable DSP block design for dynamically reconfigurable architecture

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
Reconfigurable architectures, such as Field-Programmable Gate Arrays (FPGAs), have become one of the key digital circuit implementation platform over the last decade due to its short time-to-market and low design cost. However, the major bottlenecks of FPGAs are their low logic utilization rate and long reconfiguration latency.
Rakesh Warrier, Liang Hao, Wei Zhang
openaire   +1 more source