Results 261 to 270 of about 137,190 (297)

Dynamic Defragmentation of Reconfigurable Devices

ACM Transactions on Reconfigurable Technology and Systems, 2012
We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based on dynamic relocation of module positions during runtime, with only very little reconfiguration ...
Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich   +7 more
openaire   +1 more source

Dynamic Reconfiguration in the RUNES Middleware

2006 IEEE International Conference on Mobile Ad Hoc and Sensor Sysetems, 2006
Next generation embedded systems will be composed of large numbers of heterogeneous devices. These will typically be resource-constrained (such as sensor motes), will use different operating systems, and will be connected through different types of network interfaces.
Geoff Coulson, Richard Gold, Manish Lad, Cecilia Mascolo, Luca Mottola, Gian Pietro Picco, Stefanos Zachariadis   +6 more
openaire   +3 more sources

Dynamically Reconfigurable Filtering Architectures

2010
Distributed R-trees (DR-trees) are appealing infrastructures for implementing range queries, content based filtering or k-NN structures since they inherit the features of R-trees such as logarithmic height, bounded number of neighbors and balanced shape.
Valero, Mathieu, Arantes, Luciana, Gradinariu, Maria, Sens, Pierre   +3 more
openaire   +1 more source

NoC Dynamically Reconfigurable as TAM

2012 IEEE 21st Asian Test Symposium, 2012
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUTs). To facilitate the network on chip (NoC) testing, test engineers frequently focus on reusing the NoC as TAM, in which, communication infrastructure of the NoC (routers, interconnection links ...
Takieddine Sbiai, Kazuteru Namba
openaire   +1 more source

Generator of dynamically reconfigurable processor

Artificial Life and Robotics, 2015
In recent years, demand for field-programmable gate arrays (FPGAs) has increased significantly. Designed similarly to software, FPGAs opened the door to the field of hardware for many people. However, developing a circuit using conventional methods is time consuming.
Takahiko Sega, Akinori Kanasugi, Ki Ando
openaire   +1 more source

Dynamic reconfiguration policies for reconfigurable coded-WDM PONs

Photonic Network Communications, 2006
This paper studies the issues arising when reconfiguring coded-WDM networks to provide protection against eavesdropping and it proposes a tradeoffs involved in carrying out this reconfiguration process. It commences by showing that the degree of confidentiality (DOC) and the traffic loss are two important, but conflicting, objectives in the design of ...
openaire   +1 more source

Dynamically reconfigurable microphone arrays

2011 IEEE International Conference on Robotics and Automation, 2011
Robotic sound localization has traditionally been restricted to either on-robot microphone arrays or embedded microphones in aware environments, each of which have limitations due to their static configurations. This work overcomes the static configuration problems by using visual localization to track multiple wireless microphones in the environment ...
Eric Martinson, Benjamin R. Fransen
openaire   +1 more source

Dynamic Reconfiguration in Coordination Languages

2000
A rather recent approach in programming parallel and distributed systems is that of coordination models and languages. Coordination programming enjoys a number of advantages such as the ability to express different software architectures and abstract interaction protocols, supporting multilinguality, reusability and programming-in-the-large, etc.
George A. Papadopoulos, Farhad Arbab
openaire   +1 more source

Dynamically reconfigurable protocol transducer

2006 IEEE International Conference on Field Programmable Technology, 2006
Protocol transducer synthesis is one of the most significant issues for efficient IP core reuse in SoC design. The authors proposed automatic protocol transducer synthesis method (Watanabe et al., 2006), (Ishikawa et al., 2006). In this paper, an application of the protocol synthesis method to reconfigurable architecture on FPGA was proposed that ...
Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita   +4 more
openaire   +1 more source

MVS Dynamic Reconfiguration Management

IBM Journal of Research and Development, 1992
This paper presents an overview of the Dynamic Reconfiguration Management (DRM) function of MVS/ESA™ and its support of the IBM Enterprise System/9000™ family of machines. Dynamic Reconfiguration Management is the ability to select a new I/O configuration definition without needing to perform a power-on reset (POR) of the hardware or an initial program
Richard Cwiakala, Jeffrey D. Haggar, Harry M. Yudenfriend   +2 more
openaire   +1 more source