Results 131 to 140 of about 3,085,998 (189)

Molecular basis of the urate transporter URAT1 inhibition by gout drugs. [PDF]

Nat Commun
Suo Y, Fedor JG, Zhang H, Tsolova K, Shi X, Sharma K, Kumari S, Borgnia M, Zhan P, Im W, Lee SY.   +10 more
europepmc   +1 more source

Prediction of the axial compression capacity of ECC-CES columns using adaptive sampling and machine learning techniques. [PDF]

Sci Rep
Megahed K.
europepmc   +1 more source

A biochemical sensor with continuous extended stability in vivo. [PDF]

Nat Biomed Eng
Chen Y, Fu KX, Cotton R, Ou Z, Kwak JW, Chien JC, Kesler V, Nyein HYY, Eisenstein M, Tom Soh H.   +9 more
europepmc   +1 more source

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ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories

IEEE Transactions on Computers, 2021
Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is a major concern and is of decisive importance when a higher protection capability is required to tolerate multiple adjacent bit errors (burst errors).
Soontae Kim, Hyeonggyu Kim, Hamed Farbeh
exaly   +3 more sources

VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications

IEEE Transactions on Circuits and Systems II: Express Briefs, 2014
Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word.
Swarup Bhunia, Jongsun Park
exaly   +3 more sources

Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches

IEEE Transactions on Computers, 2016
Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors.
Soontae Kim, Hyeonggyu Kim, Hamed Farbeh
exaly   +3 more sources

ECC Error Correction IP Design Based on BCH Code

Third International Symposium on Computer Engineering and Intelligent Communications (ISCEIC 2022), 2023
Ruixue Wang, Haiyang Qin, Xuena Zheng, Jiayuan Tao   +3 more
exaly   +2 more sources

CD-ECC: Content-Dependent Error Correction Codes for Combating Asymmetric Nonvolatile Memory Operation Errors

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013
Yiran Chen, Wujie Wen, Seung H Kang
exaly   +3 more sources

DBB-ECC: Random Double Bit and Burst Error Correction Code for HBM3

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Jongsun Park
exaly   +3 more sources