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Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
IEEE Transactions on Computers, 2015 To avoid data corruption, error correction codes (ECCs) are widely used to protect memories. ECCs introduce a delay penalty in accessing the data as encoding or decoding has to be performed. This limits the use of ECCs in high-speed memories.
Pedro Reviriego +2 more
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Proceedings of the International Symposium on Memory Systems, 2017
An application may have different sensitivity to faults in different subsets of the data it uses. Some data regions may therefore be more critical than others. Capitalizing on this observation, Odd-ECC provides a mechanism to dynamically select the memory fault tolerance of each allocated page of a program on demand depending on the criticality of the ...
Alirad Malek +4 more
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An application may have different sensitivity to faults in different subsets of the data it uses. Some data regions may therefore be more critical than others. Capitalizing on this observation, Odd-ECC provides a mechanism to dynamically select the memory fault tolerance of each allocated page of a program on demand depending on the criticality of the ...
Alirad Malek +4 more
openaire +2 more sources
IEEE Transactions on Computers, 2021
Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is a major concern and is of decisive importance when a higher protection capability is required to tolerate multiple adjacent bit errors (burst errors).
Hamed Farbeh +3 more
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Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is a major concern and is of decisive importance when a higher protection capability is required to tolerate multiple adjacent bit errors (burst errors).
Hamed Farbeh +3 more
openaire +2 more sources
ECC2: Error correcting code and elliptic curve based cryptosystem
Information Sciences, 2020zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Fangguo Zhang +2 more
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Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems
2019 IEEE 37th VLSI Test Symposium (VTS), 2019As memory technology scales, the demand for higher performance and reliable operation is increasing as well. For main memory, e.g., DRAM, a conventional single error correcting double error detecting (SEC-DED) code may not be sufficient. However, existing double error correcting (DEC) codes either have very high decoder latency or high data redundancy.
Abhishek Das 0005, Nur A. Touba
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VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications
IEEE Transactions on Circuits and Systems II: Express Briefs, 2014Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word.
Jangwon Park +2 more
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Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System
Journal of Signal Processing Systems, 2013With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the ...
Insoo Lee +3 more
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Error-Correcting Code (ECC) and Module Size Considerations in 2D Aztec Barcode Readability
Journal of Imaging Science and Technology, 2010Error-Correcting Code (ECC) provides robust readability to both linear and two-dimensional (2D) barcodes, particularly for localized damage. Many ECC approaches, however, are based on assumptions about the types of damage or the communication channel used.
Marie Vans, Guy Adams, Steven Simske
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ECC$$^2$$: Error Correcting Code and Elliptic Curve Based Cryptosystem
2019With the fast development of quantum computation, code-based cryptography arises public concern as a candidate for post quantum cryptography. However, the large key-size becomes a drawback such that the code-based schemes seldom become practical. Algebraic geometry codes was considered to be a good solution to reduce the size of keys, but its special ...
Fangguo Zhang, Zhuoran Zhang
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IEEE Transactions on Computers, 2016
Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors.
Hamed Farbeh +3 more
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Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors.
Hamed Farbeh +3 more
openaire +2 more sources