Results 141 to 150 of about 381 (171)

Odd-ECC

Proceedings of the International Symposium on Memory Systems, 2017
An application may have different sensitivity to faults in different subsets of the data it uses. Some data regions may therefore be more critical than others. Capitalizing on this observation, Odd-ECC provides a mechanism to dynamically select the memory fault tolerance of each allocated page of a program on demand depending on the criticality of the ...
Alirad Malek, Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis   +4 more
openaire   +1 more source

Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems

2019 IEEE 37th VLSI Test Symposium (VTS), 2019
As memory technology scales, the demand for higher performance and reliable operation is increasing as well. For main memory, e.g., DRAM, a conventional single error correcting double error detecting (SEC-DED) code may not be sufficient. However, existing double error correcting (DEC) codes either have very high decoder latency or high data redundancy.
Abhishek Das 0005, Nur A. Touba
openaire   +1 more source

VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications

IEEE Transactions on Circuits and Systems II: Express Briefs, 2014
Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word.
Jangwon Park, Jongsun Park 0001, Swarup Bhunia   +2 more
openaire   +1 more source

Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System

Journal of Signal Processing Systems, 2013
With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the ...
Insoo Lee, Jinmo Kwon, Jangwon Park, Jongsun Park 0001   +3 more
openaire   +1 more source

Error-Correcting Code (ECC) and Module Size Considerations in 2D Aztec Barcode Readability

Journal of Imaging Science and Technology, 2010
Error-Correcting Code (ECC) provides robust readability to both linear and two-dimensional (2D) barcodes, particularly for localized damage. Many ECC approaches, however, are based on assumptions about the types of damage or the communication channel used.
Marie Vans, Guy Adams, Steven Simske
openaire   +1 more source

Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches

IEEE Transactions on Computers, 2016
Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors.
Hamed Farbeh, Hyeonggyu Kim, Seyed Ghassem Miremadi, Soontae Kim   +3 more
openaire   +1 more source

ECC$$^2$$: Error Correcting Code and Elliptic Curve Based Cryptosystem

2019
With the fast development of quantum computation, code-based cryptography arises public concern as a candidate for post quantum cryptography. However, the large key-size becomes a drawback such that the code-based schemes seldom become practical. Algebraic geometry codes was considered to be a good solution to reduce the size of keys, but its special ...
Fangguo Zhang, Zhuoran Zhang
openaire   +1 more source

Method of the accelerated verification of ECC (Error — Correcting codes) codecs by means of Simulink/Matlab packet

2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), 2018
Nowadays there are a lot of software packets for simulation, modeling, debugging of hardware module description. However there are some issues related with functional testing of the algebraic blocks and algorithms. In case of comparison the designed algorithm with reference one we need a wide library of well-known proven models.
Andrey A. Belyaev, Pavel Poperechny, Irina Poperechnaya   +2 more
openaire   +1 more source

Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems [error correcting codes]

Proceedings. 10th IEEE International On-Line Testing Symposium, 2004
In this paper, we analyze the impact of error correcting codes (ECCs) on simultaneously switching outputs (SSO) noise, for the case of a realistic bus of a high reliability system. First, we analyze the effect of different bus transitions on SSO noise. Then we show how different ECCs, requiring a different number of check bits, impact the SSO noise. We
D. Rossi, A. Muccio, A.K. Nieuwland, A. Katoch, C. Metra   +4 more
openaire   +1 more source

Neutron Induced Single Event Upset (SEU) Testing of Commercial Memory Devices with Embedded Error Correction Codes (ECC)

2017 IEEE Radiation Effects Data Workshop (REDW), 2017
Results of neutron induced single event upset testing of devices with embedded error correction codes are described. Specifically, Cypress CY7C1061GE30-10BVXI and CY7C1061GE-10BVXI 16-Mbit Static Random Access Memories (SRAMs), and a memory system, consisting of a Tundra Tsi107 PowerPC Host Bridge interfacing with nine Micron MT48LC32M8A2TG-75ITD 256 ...
John M. Bird, Michael K. Peters, Travis Z. Fullem, Michael J. Tostanoski, Terrence F. Deaton, Kristianto Hartojo, Roy E. Strayer   +6 more
openaire   +1 more source