Results 141 to 150 of about 32,656 (190)
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2017 IEEE Radiation Effects Data Workshop (REDW), 2017
Results of neutron induced single event upset testing of devices with embedded error correction codes are described. Specifically, Cypress CY7C1061GE30-10BVXI and CY7C1061GE-10BVXI 16-Mbit Static Random Access Memories (SRAMs), and a memory system, consisting of a Tundra Tsi107 PowerPC Host Bridge interfacing with nine Micron MT48LC32M8A2TG-75ITD 256 ...
John M. Bird +6 more
openaire +1 more source
Results of neutron induced single event upset testing of devices with embedded error correction codes are described. Specifically, Cypress CY7C1061GE30-10BVXI and CY7C1061GE-10BVXI 16-Mbit Static Random Access Memories (SRAMs), and a memory system, consisting of a Tundra Tsi107 PowerPC Host Bridge interfacing with nine Micron MT48LC32M8A2TG-75ITD 256 ...
John M. Bird +6 more
openaire +1 more source
2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), 2018
Nowadays there are a lot of software packets for simulation, modeling, debugging of hardware module description. However there are some issues related with functional testing of the algebraic blocks and algorithms. In case of comparison the designed algorithm with reference one we need a wide library of well-known proven models.
Andrey A. Belyaev +2 more
openaire +1 more source
Nowadays there are a lot of software packets for simulation, modeling, debugging of hardware module description. However there are some issues related with functional testing of the algebraic blocks and algorithms. In case of comparison the designed algorithm with reference one we need a wide library of well-known proven models.
Andrey A. Belyaev +2 more
openaire +1 more source
IEEE Transactions on Computers, 2016
Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors.
Hamed Farbeh +3 more
openaire +1 more source
Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors.
Hamed Farbeh +3 more
openaire +1 more source
Proceedings. 10th IEEE International On-Line Testing Symposium, 2004
In this paper, we analyze the impact of error correcting codes (ECCs) on simultaneously switching outputs (SSO) noise, for the case of a realistic bus of a high reliability system. First, we analyze the effect of different bus transitions on SSO noise. Then we show how different ECCs, requiring a different number of check bits, impact the SSO noise. We
D. Rossi +4 more
openaire +1 more source
In this paper, we analyze the impact of error correcting codes (ECCs) on simultaneously switching outputs (SSO) noise, for the case of a realistic bus of a high reliability system. First, we analyze the effect of different bus transitions on SSO noise. Then we show how different ECCs, requiring a different number of check bits, impact the SSO noise. We
D. Rossi +4 more
openaire +1 more source
2019 IEEE Radiation Effects Data Workshop, 2019
Results of neutron induced single event upset testing of the Spansion (Cypress) 128Mb, 90nm, S29GL128P and 256Mb, 65nm, S25FL256S MirrorBit NOR Flash memory, the latter with embedded error correction codes, are described.Five samples of each memory type were irradiated with a 14-MeV neutron source.
Mark Allenspach +7 more
openaire +1 more source
Results of neutron induced single event upset testing of the Spansion (Cypress) 128Mb, 90nm, S29GL128P and 256Mb, 65nm, S25FL256S MirrorBit NOR Flash memory, the latter with embedded error correction codes, are described.Five samples of each memory type were irradiated with a 14-MeV neutron source.
Mark Allenspach +7 more
openaire +1 more source
International Symposium on Information Theory
Analog error-correcting codes (Analog ECCs) can effectively detect and correct computational errors generated during vector-matrix multiplication in the real domain.
Zhengyi Jiang +5 more
semanticscholar +1 more source
Analog error-correcting codes (Analog ECCs) can effectively detect and correct computational errors generated during vector-matrix multiplication in the real domain.
Zhengyi Jiang +5 more
semanticscholar +1 more source
2018
In this paper, we presented an adaptive application of forward error code (FEC) for efficient message transmission in vehicular ad hoc networks (VANETs). Our solution is a combination of automatic retransmission request (ARQ) with FEC at the MAC layer.
Shehu Jabaka Muhammad +2 more
openaire +1 more source
In this paper, we presented an adaptive application of forward error code (FEC) for efficient message transmission in vehicular ad hoc networks (VANETs). Our solution is a combination of automatic retransmission request (ARQ) with FEC at the MAC layer.
Shehu Jabaka Muhammad +2 more
openaire +1 more source
ECC error correction IP design based on BCH code
Third International Symposium on Computer Engineering and Intelligent Communications (ISCEIC 2022), 2023Ruixue Wang +3 more
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Efficient implementation of error correction codes in hash tables
Microelectronics and reliability, 2014Hash tables are one of the most commonly used data structures in computing applications. They are used for example to organize a data set such that searches can be performed efficiently.
P. Reviriego +3 more
semanticscholar +1 more source
Improving DRAM Reliability Using a High Order Error Correction Code
IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDynamic random access memory (DRAM) is being upgraded iteratively, and as a result, its transmission rate and bandwidth are rising quickly. Simultaneously, as the DRAM process has advanced, the storage cell size has decreased and cell integration has ...
Wei Li +5 more
semanticscholar +1 more source