Results 61 to 70 of about 2,530,044 (192)
Concurrency and Computation: Practice and Experience, Volume 38, Issue 16, August 2026.ABSTRACT Photonic matrix processors are attracting attention in applications such as AI inference due to their low‐power and low‐latency properties. However, their applicability has been largely limited to low‐precision computation due to inherent stochastic analog noise and device non‐idealities.
Shoichi Hirasawa, Michihiro Koibuchi
wiley +1 more source
Convolutional Codes for Network-Error Correction
, 2009 In this work, we introduce convolutional codes for network-error correction in the context of coherent network coding. We give a construction of convolutional codes that correct a given set of error patterns, as long as consecutive errors are separated ...
Rajan, Sundar B, Prasad, K
core
Quantum Error Correction via Codes over GF(2)
, 2009 It is well known that n-length stabilizer quantum error correcting codes (QECCs) can be obtained via n-length classical error correction codes (CECCs) over GF(4), that are additive and self-orthogonal with respect to the trace Hermitian inner product ...
Chowdhury, Arijit +4 more
core +1 more source
Coding Techniques for Data-Storage Systems [PDF]
, 2008 As information-bearing objects, data-storage systems are natural consumers of information-theoretic ideas. For many issues in data-storage systems, the best trade-off between cost, performance and reliability, passes through the application of error ...
Cassuto, Yuval
core +1 more source
, 2004 We propose a generic algorithm for the construction of efficient reversible variable-length codes (RVLCs) and variable-length error-correcting (VLEC) codes, which optimizes the codeword length distribution.
Wang, J., Yang, L-L., Hanzo, L.
core +1 more source
Physical Unclonable Function Based on 3D‐NAND Flash Array Structure With Multi‐Chip Implementation
Small, Volume 22, Issue 45, 13 August 2026.Physical unclonable function (PUF) based on a 3D‐NAND flash array is proposed, featuring a multi‐chip structure and a massive challenge–response pair (CRP) capacity. The presented utilizes intrinsic string current variations experimentally verified across eight fabricated 48 × 24 NAND flash arrays.
Hwiho Hwang +4 more
wiley +1 more source
Nonlinear error correction, asymmetric adjusment and cointegration [PDF]
, 1991 This paper has three main components. First, it outlines a model of nonlinear error correction (NEC) in which the linear error correction term a'Xt (the vector time series Xt is cointegrated, a is the cointegrating vector) is replaced by the nonlinear ...
Pfann, Gerard, Escribano, Álvaro
core +1 more source
Expanding window fountain codes for unequal error protection [PDF]
, 2007 A novel approach to provide unequal error protection (UEP) using rateless codes over erasure channels, named Expanding Window Fountain (EWF) codes, is developed and discussed.
Vukobratovic, D +11 more
core +1 more source
Error correcting code analysis for cache memory high reliability and performance
In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead ...
Metra, Cecilia +3 more
core +1 more source
Concatenated Turbo/LDPC codes for deep space communications: performance and implementation [PDF]
, 2013 Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals.
Condo, Carlo
core