Results 11 to 20 of about 2,049,776 (246)
Interposer-Based ESD Protection: A Potential Solution for μ-Packaging Reliability of 3D Chips [PDF]
MicromachinesThe ending of Moore’s Law calls for innovations in integrated circuit (IC) technologies and chip designs. Heterogeneous integration (HI) emerges as a pathway towards smart future chips for more Moore time and for beyond-Moore time, featuring systems-on ...
Xunyu Li +5 more
doaj +2 more sources
SCR-Based ESD Protection Using a Penta-Well for 5 V Applications
IEEE Journal of the Electron Devices Society, 2018 This paper proposes a new structure of silicon controlled rectifier (SCR)-based ESD protection circuit using a penta-well for ESD protection in 5 V applications. The proposed circuit exhibits higher holding voltage and current-driving capability than low
Bo-Bae Song, Kyoung-Il Do, Yong-Seo Koo
doaj +2 more sources
Novel Bidirectional ESD Circuit for GaN HEMT [PDF]
MicromachinesIn this paper, the ESD protection circuit for p-GaN gate HEMTs with bidirectional clamp is proposed and investigated. ESD clamp circuits consist of several forward diodes in serials and a reverse diode.
Pengfei Zhang +7 more
doaj +2 more sources
Physics of electro-thermal effects in ESD protection devices [PDF]
, 1991 Damage in ESD protection devices can be caused by high local temperatures resulting from heat generation by an ESD pulse. In order to obtain physical insight into the process that leads to permanent damage, device simulations of coupled thermal and ...
Beltman, R.A.M. +3 more
core +25 more sources
Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network
Crystals, 2021 The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network.
Zhihua Zhu +5 more
doaj +1 more source
ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation
IEEE Journal of the Electron Devices Society, 2021 Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs.
Mengfu Di +3 more
doaj +1 more source
On-chip ESD Protection Design Methodologies by CAD Simulation
ACM Trans. Design Autom. Electr. Syst., 2023 Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs). On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional
Zijin Pan +4 more
semanticscholar +1 more source
Delayed Duodenal Ulcer Perforation Following Esophageal Endoscopic Submucosal Dissection Complicated by Perforation: A Case Report. [PDF]
DEN OpenAbstract Endoscopic submucosal dissection (ESD) is an established treatment of superficial esophageal neoplasms. Common complications include bleeding, perforation, and stricture. However, delayed gastrointestinal perforation distant from the ESD site is exceptionally rare.
Nakatani S +9 more
europepmc +2 more sources
IEEE Journal of the Electron Devices Society, 2023 The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by
Yi-Chun Huang, Ming-Dou Ker
doaj +1 more source
TCAD Simulation Study of ESD Behavior of InGaAs/InP Heterojunction Tunnel FETs
Crystals, 2020 For the first time, we investigated the electrostatic discharge (ESD) behavior of an InGaAs/InP heterojunction tunneling field effect transistor (HTFET). The device structure in this study has a high on-state current without extra process steps.
Zhihua Zhu +5 more
doaj +1 more source