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Diagnosing Resistive Open Faults Using Small Delay Fault Simulation
2013 22nd Asian Test Symposium, 2013Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults.
Koji Yamazaki +6 more
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Dynamic behavior of resistive faults in nanometer technology
Microelectronics Reliability, 2007Modeling the dynamic behavior for resistive shorts and opens at switch-level dictates the characterization of enhanced delay due to these faults with respect to the input combinations, fault sites, defect resistance and technology variation. The resistive fault model is applied to CMOS technologies with feature sizes of 350 nm, 180 nm, 90 nm, 45 nm and
Mayuri Kunchwar +2 more
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Fault-resistance effect on ground fault current
Electrical Engineering, 1953GROUND FAULT currents may be reduced substantially when fault resistance is included in the fault circuit. The majority of faults that occur on a power system involve ground and occur between conductor and tower. When a fault occurs to a steel tower or grounded wood pole on a grounded system the footing resistance is included automatically in the fault
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PROBE: a PPSFP simulator for resistive bridging faults
Proceedings 18th IEEE VLSI Test Symposium, 2002Bridging faults in CMOS circuits are usually modeled as a wired-OR, wired-AND, or small fixed resistance. Real bridging faults have a resistance distribution ranging from very small to quite large. The parametric model has been proposed to handle this resistance distribution, along with table-oriented approaches that are accurate and fast.
Chul Young Lee, D. M. H. Walker
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A fault-tolerant, DFA-resistant AES core
2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008In this work we analyze four techniques to protect a cryptographic core, which can be combined to allow for several implementations with different area overheads and protection levels. Experimental results show their efficiency in protecting the core against fault attacks, while being flexible enough to leave other design aspects to be explored by the ...
Carlos Roberto Moratelli +3 more
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The ‘quarter-power equation’ for resistive heating faults
Science & Justice, 2022The ubiquitous nature of electricity makes an electrical fault a primary consideration at the start of almost every fire investigation. Principal amongst the types of faults that can cause a fire is the resistive heating fault. While methods for calculating the maximum power transfer from a supply to a load are well known to electrical engineers ...
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A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems, 2003Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits.
Zhuo Li 0001 +4 more
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Intermittent Resistance Fault Detection at Board Level
2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018Interconnection reliability issues threat the dependability of highly dependable systems. One of the most challenging interconnection-induced reliability threats is intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months.
Ebrahimi, Hassan, Kerkhoff, Hans G.
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Resistive bridging fault simulation of industrial circuits
Proceedings of the conference on Design, automation and test in Europe, 2008We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnitude of the run times for pattern-parallel complete-circuit stuck-at fault simulation.
Piet Engelke +3 more
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Responses of Resistive Superconducting-Fault-Current-Limiters to Unbalanced Faults
IEEE Transactions on Appiled Superconductivity, 2005We analyzed the unsymmetrical fault characteristics of resistive superconducting-fault-current-limiters (SFCL) based on YBCO thin films with the unbalanced faults such as a single line-to-ground fault, a double line-to-ground fault, and a line-to-line fault in a three-phase system. The unsymmetrical rates of fault phases were 6.4, 9.2, 8.8 at the fault
H.-S. Choi +6 more
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