Results 281 to 290 of about 22,911 (308)

A fault-tolerant, DFA-resistant AES core

2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008
In this work we analyze four techniques to protect a cryptographic core, which can be combined to allow for several implementations with different area overheads and protection levels. Experimental results show their efficiency in protecting the core against fault attacks, while being flexible enough to leave other design aspects to be explored by the ...
Carlos Roberto Moratelli, Felipe Ghellar, Érika F. Cota, Marcelo Lubaszewski   +3 more
openaire   +1 more source

A circuit level fault model for resistive bridges

ACM Transactions on Design Automation of Electronic Systems, 2003
Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits.
Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker   +4 more
openaire   +1 more source

Resistive bridging fault simulation of industrial circuits

Proceedings of the conference on Design, automation and test in Europe, 2008
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnitude of the run times for pattern-parallel complete-circuit stuck-at fault simulation.
Piet Engelke, Ilia Polian, Juergen Schloeffel, Bernd Becker   +3 more
openaire   +1 more source

Intermittent Resistance Fault Detection at Board Level

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018
Interconnection reliability issues threat the dependability of highly dependable systems. One of the most challenging interconnection-induced reliability threats is intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months.
Ebrahimi, Hassan, Kerkhoff, Hans G.
openaire   +2 more sources

Responses of Resistive Superconducting-Fault-Current-Limiters to Unbalanced Faults

IEEE Transactions on Appiled Superconductivity, 2005
We analyzed the unsymmetrical fault characteristics of resistive superconducting-fault-current-limiters (SFCL) based on YBCO thin films with the unbalanced faults such as a single line-to-ground fault, a double line-to-ground fault, and a line-to-line fault in a three-phase system. The unsymmetrical rates of fault phases were 6.4, 9.2, 8.8 at the fault
H.-S. Choi, S.-H. Lim, D.-C. Chung, B.-S. Han, O.-B. Hyun, T.-H. Sung, J.-S. Hwang   +6 more
openaire   +1 more source

The electrical resistivity of stacking faults

Philosophical Magazine, 1960
Abstract The scattering of electrons and x-rays by stacking faults is due to a phase change in the diffraction by crystal planes which do not lie parallel to the fault. A simple model of the process in copper estimates a resistivity p≃1 × 10−12 β ohm-cm for a total stacking fault density of β cm−1 on all planes.
openaire   +1 more source

Modeling feedback bridging faults with non-zero resistance

The Eighth IEEE European Test Workshop, 2003. Proceedings., 2004
We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance.
Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker 0001   +3 more
openaire   +2 more sources

Automatic test pattern generation for resistive bridging faults

Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004., 2004
An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults ...
Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001   +3 more
openaire   +3 more sources

Aspects of the Development of Secure and Fault-Resistant Hardware

2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008
Designing "secure hardware" like a chip card controller, is a challenging task for hardware manufacturers: More and more attacks that are also more and more sophisticated generate a need for more and more countermeasures. Developers of these devices have to live with certain additional constraints and this does not make their life easier.
openaire   +1 more source

Faulty resistance sectioning technique for resistive bridging fault ATPG systems

Proceedings 10th Asian Test Symposium, 2002
This paper proposes a bridging fault resistance sectioning technique for high speed generation systems of test sets which detect all the resistive bridging faults detectable by logic testing, targeting all the resistive bridging faults each of which ranges from zero ohm to infinity resistance. The previously proposed ATPG systems for this problem dealt
Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi   +4 more
openaire   +1 more source