Results 71 to 80 of about 132,738 (209)

Random background charges and Coulomb blockade in one-dimensional tunnel junction arrays [PDF]

open access: yesPhys. Rev. B 63, 014201 (2001), 2000
We have numerically studied the behavior of one dimensional tunnel junction arrays when random background charges are included using the ``orthodox'' theory of single electron tunneling. Random background charge distributions are verified in both amplitude and density. The use of a uniform array as a transistor is discussed both with and without random
arxiv   +1 more source

Digital model of TiO(2) memristor for field-programmable gate array

open access: yesThe Journal of Engineering, 2014
A digital model which imitates the behaviour of a TiO(2) memristor as a new block in Alter DSP Builder is proposed in this Letter. The proposed model can be used as an independent memristor unit working with other units for designing memristor circuits ...
Guangyi Wang, Dandan Bai, Xiaoyuan Wang
doaj   +1 more source

Corrigendum

open access: yesAdvances in Mechanical Engineering, 2016
CORRIGENDUM A hybrid swarm intelligence of artificial immune system tuned with Taguchi–genetic algorithm and its field-programmable gate array realization to optimal inverse kinematics for an articulated industrial robotic manipulator Owing to errors ...
doaj   +1 more source

InSight: An FPGA-Based Neuromorphic Computing System for Deep Neural Networks

open access: yesJournal of Low Power Electronics and Applications, 2020
Deep neural networks have demonstrated impressive results in various cognitive tasks such as object detection and image classification. This paper describes a neuromorphic computing system that is designed from the ground up for energy-efficient ...
Taeyang Hong   +2 more
doaj   +1 more source

Multi-exposure laser speckle contrast imaging using a high frame rate CMOS sensor with a field programmable gate array.

open access: yesOptics Letters, 2015
A system has been developed in which multi-exposure laser speckle contrast imaging (LSCI) is implemented using a high frame rate CMOS imaging sensor chip. Processing is performed using a field programmable gate array (FPGA).
Shen Sun   +4 more
semanticscholar   +1 more source

A novel method based solely on field programmable gate array (FPGA) units enabling measurement of time and charge of analog signals in positron emission tomography (PET) [PDF]

open access: yesBio Algorithms Med Syst., 2013
This article presents an application of a novel technique for precise measurements of time and charge based solely on a field programmable gate array (FPGA) device for positron emission tomography (PET).
M. Palka   +25 more
semanticscholar   +1 more source

Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

open access: yesIEEE Access, 2019
Phasor Measurement Units (PMUs) are becoming intrinsic components of modern power systems. The synchrophasor estimation algorithms in PMUs pose stringent computational demands, which makes the application of Field Programmable Gate Arrays (FPGA) highly ...
Prottay M. Adhikari   +2 more
doaj   +1 more source

Ultrafast jet classification at the HL-LHC

open access: yesMachine Learning: Science and Technology
Three machine learning models are used to perform jet origin classification. These models are optimized for deployment on a field-programmable gate array device.
Patrick Odagiu   +15 more
doaj   +1 more source

Field programmable gate array based predictive control system for spacecraft rendezvous in elliptical orbits

open access: yes, 2015
A field programmable gate array (FPGA) based model predictive controller for two phases of spacecraft rendezvous is presented. Linear time‐varying prediction models are used to accommodate elliptical orbits, and a variable prediction horizon is used to ...
Edward N. Hartley, J. Maciejowski
semanticscholar   +1 more source

Implementation of Reed-Solomon Encoder/Decoder Using Field Programmable Gate Array

open access: yesJournal of Engineering and Sustainable Development, 2006
In this paper, (15, 11) and (255, 239) Reed-Solomon codes have been designed and Implemented using ALTERA Field Programmable Gate Array (FPGA) device. The design is carried out by writing VHDL modules for different encoder and decoder components.
Hikmat N. Abdullah
doaj  

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