Results 1 to 10 of about 1,953 (70)

FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design

open access: yesMicromachines, 2021
In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, by using which the circuit of AND gate and OR gate composed of memristors is built. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate
Liu Yang   +3 more
doaj   +1 more source

Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms [PDF]

open access: yesInternational Journal of Computational Intelligence Systems, 2011
This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT) suitable for electronic warfare (EW) applications.
He Chen   +3 more
doaj   +1 more source

Wykorzystanie struktur FPGA do implementacji algorytmów cyfrowego przetwarzania sygnałów [PDF]

open access: yesProblemy Mechatroniki, 2017
W artykule opisano zaprojektowany, wykonany praktycznie oraz przebadany dwukanałowy tor cyfrowego przetwarzania sygnału z układem FPGA (Field-Programmable Gate Array), w którym zaimplementowano algorytmy DSP.
Stanisław GRZYWIŃSKI   +1 more
doaj   +1 more source

An efficient AES implementation using FPGA with enhanced security features

open access: yesJournal of King Saud University: Engineering Sciences, 2020
Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for secure communication, a new Hybrid non pipelined Advanced Encryption Standard (AES) algorithm based on traditional AES algorithm with enhanced security ...
Harshali Zodpe, Ashok Sapkal
doaj   +1 more source

High-resolution FPGA-pulse width modulation applied to PFC 2 MHz converter using eGaN field effect transistor

open access: yesThe Journal of Engineering, 2019
This study proposes an implementation based on a low-cost field-programmable gate array (FPGA) of a high-resolution pulse width modulation applied on a single-phase power factor correction (PFC) converter operating with 2 MHz switch frequency.
José Augusto Arbugeri   +2 more
doaj   +1 more source

Implementation of the block cipher Rijndael using Altera FPGA

open access: yesJournal of Telecommunications and Information Technology, 2001
A short description of the block cipher Rijndael is presented. Hardware implementation by means of the FPGA (field programmable gate array) technology is evaluated. Im- plementation results compared with other hardware imple- mentations are summarized.
Piotr Mroczkowski
doaj   +1 more source

Robust Direct Torque Control with Super-Twisting Sliding Mode Control for an Induction Motor Drive

open access: yesComplexity, 2019
A field-programmable gate array- (FPGA-) based nonlinear Direct Torque Control (DTC) associated with Space Vector Modulation (SVM), Input-Output Feedback Linearization (IOFL), and second-order super-twisting speed controller is proposed to control an ...
Saber Krim   +2 more
doaj   +1 more source

Design of a novel multi-channel general signal processing platform

open access: yesDianzi Jishu Yingyong, 2019
This paper presented the design of a novel general signal processing system based on the partial reconfiguration of Field Programmable Gate Array(FPGA). This solution uses framework of high speed FPGA,Digital Signal Processor(DSP) and Analog/Digital ...
Zheng Baiheng   +3 more
doaj   +1 more source

A Portable Laser Photoacoustic Methane Sensor Based on FPGA

open access: yesSensors, 2016
A portable laser photoacoustic sensor for methane (CH4) detection based on a field-programmable gate array (FPGA) is reported. A tunable distributed feedback (DFB) diode laser in the 1654 nm wavelength range is used as an excitation source.
Jianwei Wang, Huili Wang, Xianyong Liu
doaj   +1 more source

Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

open access: yesSensors, 2014
This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm.
Alisson C. D. de Souza   +1 more
doaj   +1 more source

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