Results 51 to 60 of about 47,640 (336)
Design of FPGA-Based LZ77 Compressor With Runtime Configurable Compression Ratio and Throughput
IEEE Access, 2019 Data compression reduces the cost of data storage and transmission by decreasing the data size. Previous studies have improved system performance by adaptively choosing the compression ratio (CR) and throughput required for the system by using a trade ...
Seungdo Choi +6 more
doaj +1 more source
Embedded control system Compact RIO in vibration measurement [PDF]
, 2012 Bakalářská práce se zabývá měřením vibrací na programovatelném hradlovém poli Compact RIO, pomocí měřící aplikace vytvořené v grafickém vývojovém prostředí LabVIEW. V práci jsou popsány možnosti měření vibrací a dostupné prostředky.
Pšenčík, Petr
core
, 2017 The Belle II detector at the SuperKEKB accelerator has a level 1 trigger implemented in field-programmable gate arrays. Due to the high luminosity of the beam, a trigger that effectively rejects beam induced background is required.
Kim, J. B., Ko, B. R., Won, E.
core +1 more source
Network on chip architecture for multi-agent systems in FPGA [PDF]
, 2017 A system of interacting agents is, by definition, very demanding in terms of computational resources. Although multi-agent systems have been used to solve complex problems in many areas, it is usually very difficult to perform large-scale simulations in ...
Belatreche, A +3 more
core +4 more sources
Receptor‐Free Identification of Toxic Gases Enabled by Hygroscopic Aqueous Salt Films
Advanced Functional Materials, EarlyView.Water as a gas sensor coating sounds impossible—until it stops evaporating. Here, hygroscopic salt solutions (LiCl, LiBr, H3PO4) form non‐drying aqueous films on CNT chemiresistors under ambient air. Gases partition into these liquid layers, sometimes transforming into water, and generate salt‐specific resistance fingerprints across a four‐channel ...
Seongwoo Lee +5 more
wiley +1 more source
The NAIL Accelerator Interface Layer for Low Latency FPGA Offload
IEEE AccessWe present the NAIL Accelerator Interface Layer, a framework for offloading accelerated computations to Field Programmable Gate Arrays served across the network.
Edward Grindley +8 more
doaj +1 more source
On the Use of Magnetic RAMs in Field-Programmable Gate Arrays
International Journal of Reconfigurable Computing, 2008 This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design.
Y. Guillemenet +3 more
doaj +1 more source
FPGA Based Real Time Simulations of the Face Milling Process
IEEE Access, 2020 The article presents a successful implementation of the milling process simulation at the Field-Programmable Gate Array (FPGA). By using FPGA, very rigorous Real-Time (RT) simulation requirements can be met.
Michal R. Mazur +2 more
doaj +1 more source
Multi‐Scale Interface Engineering of MXenes for Multifunctional Sensory Systems
Advanced Functional Materials, EarlyView.MXenes, as two‐dimensional transition metal carbides and nitrides, demonstrate remarkable capabilities for multifunctional sensing applications. This review systematically examines multi‐scale interface engineering approaches that enhance sensing performance, enable diverse detection functionalities, and improve system‐level compatibility in MXene ...
Jiaying Liao, Sin‐Yi Pang, Jianhua Hao
wiley +1 more source
Various anti-fuse structures for field programmable gate arrays and programmable read-only memories
Доклады Белорусского государственного университета информатики и радиоэлектроники, 2019 The use of anti-fuses as programmable elements is becoming popular in field programmable gate arrays and programmable read-only memories. The characteristics of various structures of anti-fuses and compromise between performance and reliability will be ...
V. A. Petrovich +3 more
doaj