Results 41 to 50 of about 11,759 (260)
Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation
International Journal of Reconfigurable Computing, 2008 This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an ...
Johan Ditmar +2 more
doaj +1 more source
Design of FPGA-Based LZ77 Compressor With Runtime Configurable Compression Ratio and Throughput
IEEE Access, 2019 Data compression reduces the cost of data storage and transmission by decreasing the data size. Previous studies have improved system performance by adaptively choosing the compression ratio (CR) and throughput required for the system by using a trade ...
Seungdo Choi +6 more
doaj +1 more source
A lean FPGA soft processor built using a DSP block
, 2012 As Field Programmable Gate Arrays (FPGAs) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for FPGA adoption, so FPGA vendors tailored ...
Hui Yan Cheah +7 more
core +1 more source
Multidimensional Cellular Micro‐Compartments to Model Invasive Lobular Carcinoma Dormancy
Advanced Healthcare Materials, EarlyView.Invasive lobular carcinoma (ILC) is an understudied subtype of breast cancer that is susceptible to late recurrences. In this study, micro‐compartmentalization techniques spanning multiple dimensions, including 2D, pseudo‐3D, and 3D, are integrated to uncover the mechanisms underlying ILC dormancy, revealing the central role of p27Kip1.
Xilal Y. Rima +15 more
wiley +1 more source
Frequency Synchronization for Wireless Networks using Field Programmable Gate Arrays [PDF]
, 2016 Final version published as: Markus Appel, Felix Wermke, Frank Winkler, Beate Meffert: Frequency Synchronization for Wireless Networks using Field Programmable Gate Arrays. In: 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Winkler, Frank +3 more
core +1 more source
The NAIL Accelerator Interface Layer for Low Latency FPGA Offload
IEEE AccessWe present the NAIL Accelerator Interface Layer, a framework for offloading accelerated computations to Field Programmable Gate Arrays served across the network.
Edward Grindley +8 more
doaj +1 more source
On the Use of Magnetic RAMs in Field-Programmable Gate Arrays
International Journal of Reconfigurable Computing, 2008 This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design.
Y. Guillemenet +3 more
doaj +1 more source
FPGA Based Real Time Simulations of the Face Milling Process
IEEE Access, 2020 The article presents a successful implementation of the milling process simulation at the Field-Programmable Gate Array (FPGA). By using FPGA, very rigorous Real-Time (RT) simulation requirements can be met.
Michal R. Mazur +2 more
doaj +1 more source
Advanced Healthcare Materials, EarlyView.This review examines how cellular behavior is regulated by mechanical cues transmitted through soft biomaterials, from single‐cell mechanosensing to tissue‐level adaptation. It highlights why physiological relevance, rather than model complexity alone, is critical for translational mechanobiology and introduces a scoring framework linking material ...
Mathias Polz +9 more
wiley +1 more source
Optimization of 2-d lattice cellular automata for pseudorandom number generation
, 2005 This paper proposes a generalized approach to 2-d CA PRNGs – the 2-d lattice CA PRNG – by introducing vertical connections to arrays of 1-d CA. The structure of a 2-d lattice CA PRNG lies in between that of 1-d CA and 2-d CA grid PRNGs.
Quieta, M.T.R. +3 more
core +1 more source