Results 21 to 30 of about 11,759 (260)

Testing for the programming circuit of LUT-based FPGAs

, 1997
The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs ...
T. Inoue, Okamoto, Takuji, H. Michinishi, Yokohira, Tokumi, Inoue, Tomoo, T. Yokohira, T. Okamoto, Michinishi, Hiroyuki, Fujiwara, Hideo, H. Fujiwara   +9 more
core   +1 more source

Field Programmable Gate Arrays (FPGAs) II [PDF]

, 2020
This Edited Volume Field Programmable Gate Arrays (FPGAs) II is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Computer and Information Science.

core   +1 more source

A Tag Based Random Order Vector Reduction Circuit

IEEE Access, 2020
Vector reduction is a very common operation to reduce a vector into a single scalar value in many scientific and engineering application scenarios. Therefore a fast and efficient vector reduction circuit has great significance to the real-time system ...
Yihua Huang, Wenjin Huang, Rui Chen, Huangtao Wu, Ming Wei   +4 more
doaj   +1 more source

Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

Sensors, 2016
The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing.
Nuno Brito, Carlos Ferreira, Filipe Alves, Jorge Cabral, João Gaspar, João Monteiro, Luís Rocha   +6 more
doaj   +1 more source

Integration of Low‐Voltage Nanoscale MoS2 Memristors on CMOS Microchips

Advanced Functional Materials, EarlyView.
This article presents the first monolithic integration of nanoscale MoS2‐based memristors into the back‐end‐of‐line of foundry‐fabricated CMOS microchips in a one‐transistor‐one‐resistor (1T1R) architecture. The MoS2‐based 1T1R cells exhibit forming‐free, nonvolatile resistive switching with ultra‐low operating voltages, low cycle‐to‐cycle variability ...
Jimin Lee, Sofía Cruces, Xiaohua Liu, Yang Chen, Vasilis A. Maroufidis, Janghyun Jo, Lukas Völkel, Dennis Braun, Michael Möller, Leon Brackmann, Holger Kalisch, Michael Heuken, Andrei Vescan, Rafal E. Dunin‐Borkowski, Joachim Mayer, Stefan Wiefels, Max C. Lemme   +16 more
wiley   +1 more source

FPGA-based dual-layer authentication scheme utilizing AES and ECC for unmanned aerial vehicles

EURASIP Journal on Wireless Communications and Networking
Unmanned aerial vehicles, commonly known as drones, face unique authentication challenges due to their distinct characteristics and operational environments.
Kumar Sekhar Roy, Murikipudi Sujith, Bandi Bhanu, Preethi, Ruhul Amin Hazarika   +4 more
doaj   +1 more source

Field-Programmable Gate Arrays

, 1992
Field-Programmable Gate Arrays (FPGAs) have emerged as an attractive means of implementing logic circuits, providing instant manufacturing turnaround and negligible prototype costs.
Jonathan Rose, Francis, Robert J., Rose, Jonathan 1938-, Vranesic, Zvonko G., Stephen D. Brown, Zvonko G. Vranesic, Brown, Stephen D., Robert J. Francis   +7 more
core   +1 more source

Optoelectronic Synaptic Devices Using Molecular Telluride Phase‐Change Inks for Three‐Factor Learning

Advanced Functional Materials, EarlyView.
Optoelectronic synaptic devices based on solution‐processed molecular telluride GST‐225 phase‐change inks are demonstrated for three‐factor learning. A global optical signal broadcast through a silicon waveguide induces non‐volatile conductance updates exclusively in locally electrically flagged memristors.
Kevin Portner, Dhananjeya Kumaar, Giacomo Torti, Killian Keller, Till Zellweger, Florian M. Schenk, Christoph Weilenmann, Daniel Chelladurai, Vara Prasad Jonnalagadda, Ghazi Sarwat Syed, Vanessa Wood, Jürg Leuthold, Alexandros Emboras, Maksym Yarema, Mathieu Luisier   +14 more
wiley   +1 more source

Many-body computing on Field Programmable Gate Arrays

Communications Physics
Improving many-body computational efficiency is crucial for exploring condensed matter systems. However, existing acceleration methods are limited and mostly based on von Neumann-like architectures. Here we leverage the capabilities of Field Programmable
Songtai Lv, Yang Liang, Yuchen Meng, Xiaochen Yao, Jincheng Xu, Yang Liu, Qibin Zheng, Haiyuan Zou   +7 more
doaj   +1 more source

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

, 2008
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA.
Philip Brisk, Frank K. Gurkaynak, Ajay K. Verma, Yusuf Leblebici, Alessandro Cevrero, Verma, Ajay K., Cevrero, Alessandro, Athanasopoulos, Panagiotis, Leblebici, Yusuf, Paolo Ienne, Brisk, Philip, Ienne, Paolo, Parandeh-Afshar, Hadi, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Gurkaynak, Frank K.   +15 more
core   +1 more source