Algorithmic and Theoretical Problems Related to the Physical Design of Three Dimensional Field Programmable Gate Arrays [PDF]
, 2000 John Karro
openalex +1 more source
Implementasi Discrete Cosine Transform Pada Field Programmable Gate Array [PDF]
, 2014 Pengurangan jumlah perkalian, merupakan suatu cara untuk menghasilkan komputasi cepat Discrete Cosine Transform (DCT). Algoritma 1-D DCT Loeffler merupakan modifikasi dari persamaan 1-D DCT klasik yang mampu meminimumkan penggunaan operasi perkalian dari
Mochammad Rif'an, ST., MT., Yan Felix Monangin., Waru Djuriatno, ST., MT
core
A parallel Viterbi decoder for block cyclic and convolution codes
, 2006 We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed 4 for BCH codes.
Amarasinghe, Kosala, Reeve, Jeffrey
core +2 more sources
Field Programmable Gate Arrays with Hardwired Networks on Chip [PDF]
, 2012 Technology down-scaling and platform-based designs have enforced a number of application and architecture trends for system-on-chip (SOC) designs. A modern SOC is now a multi-functional machine that can execute a large number of complex applications by using tens or even hundreds of intellectual properties (IPs).
openaire +3 more sources
Fingerprinting techniques for field-programmable gate array intellectual property protection [PDF]
, 2001 John Lach +2 more
openalex +1 more source
Routing architectures for hierarchical field programmable gate arrays [PDF]
, 2002 Aneesh Aggarwal, David Lewis
openalex +1 more source
A High-Performance and Cost-Effective Field Programmable Gate Array-Based Motor Drive Emulator. [PDF]
Micromachines (Basel), 2023 Hernandez J +2 more
europepmc +1 more source
Biasing and Demodulation Firmware for Kilopixel TES Bolometer Arrays [PDF]
arXiv, 2010 We describe the signal-processing firmware and software for a frequency-domain multiplexed (FDM) biasing and demodulation system that reads out Transition Edge Sensor (TES) bolometer arrays for mm-wavelength cosmology telescopes. This system replaces a mixed-signal readout backend with a much smaller, more power-efficient system relying on Field ...
arxiv
Relocatable Field Programmable Gate Array Bitstreams for Fault Tolerance [PDF]
, 2011 A Field Programmable Gate Array (FPGA) circuit capable of operating through at least one fault. The FPGA circuit includes a configuration memory and an embedded microprocessor. The embedded microprocessor having access to the configuration memory, static
Baldwin, Rusty O. +2 more
core +1 more source
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays [PDF]
, 2004 Steven J. E. Wilton +2 more
openalex +1 more source