Results 251 to 260 of about 72,223 (293)

Image processing on Field Programmable Gate Arrays

2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015
At present, the relevancy to image processing is increasing and applications of image processing are developing. Also “Field Programmable Gate Arrays (FPGA)” is gaining in popularity nowadays. FPGAs are strong in parallel computation and then can work too fast.
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Synthesis method for field programmable gate arrays

Proceedings of the IEEE, 1993
Logic synthesis algorithms and methods for field-programmable gate arrays (FPGAs) are reviewed. The three most popular types of FPGA architectures are considered, namely, those using logic blocks based on lookup-tables, multiplexers, and wide AND/OR arrays, respectively.
Alberto L. Sangiovanni-Vincentelli, Abbas El Gamal, Jonathan Rose   +2 more
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Field Programmable Gate Arrays

2019
The chapter deals with field-programmable gate arrays (FPGA). The basic stages are shown concerning evolution of programmable logic (from PROMs and PLAs to FPGAs). Next, the evolution of FPGAs is analysed. Three ages of FPGAs are shown. Next, the modern FPGAs produced by Xilinx and Intel (Altera) The last section is devoted to design methods targeting ...
Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz   +2 more
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Logic synthesis for field-programmable gate arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding.
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang   +3 more
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Implementing division with field programmable gate arrays

Journal of VLSI signal processing systems for signal, image and video technology, 1994
This article presents a method to map digit-recurrence arithmetic algorithms to lookup-table based Field Programmable Gate Arrays (FPGAs). By reducing the number of binary inputs to combinational logic and merging algorithm steps, the strategy creates new simplified functions to decrease logic depth and area.
Marianne E. Louie, Milos D. Ercegovac
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RSA Acceleration with Field Programmable Gate Arrays

1999
An efficient implementations of modular exponentiation, i.e., the main building block in the RSA cryptographic scheme, is achieved by first designing a bit-level systolic array such that the whole procedure of modular exponentiation can be carried out entirely by a single unit without using global interconnections or memory to store intermediate ...
Alexander Tiountchik, Elena Trichina
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Reconfigurable processing with field programmable gate arrays

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96, 2002
In-system-programmable, SRAM-based Field Programmable Gate Arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the needs of a given application. Exploiting the inherent speed and parallelism of a hardware solution, FPGA-based coprocessors can execute ...
Bradly K. Fawcett, J. Watson
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Parallel placement for field-programmable gate arrays

Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03, 2003
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we use the negotiation-based paradigm to parallelize placement. Our new FPGA placer, NAP (Negotiated Analytical Placement), uses an analytical technique for coarse placement and ...
Pak K. Chan, Martine D. F. Schlag
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Field-Programmable Gate Arrays

2016
Now comes the “hard” part. The next three chapters are all about hardware, which covers a wide gamut of topics like FPGA, SOPC, LCD, etc. This chapter begins with an overview of the embedded hardware in general, followed by detailed discussions about FPGA and IP protection.
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FIR filters with field-programmable gate arrays

Journal of VLSI signal processing systems for signal, image and video technology, 1993
Distributed arithmetic techniques are the key to efficient implementation of DSP algorithms in FPGAs. The distributed arithmetic process is briefly described. A representative DSP design application in the form of an 8 tap FIR filter is offered for the Xilinx XC3042 field programmable logic array (FPGA).
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