A parallel Viterbi decoder for block cyclic and convolution codes [PDF]
, 2005 We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed 4 for BCH codes.
Amarasinghe, Kosala, Reeve, Jeffrey
core +2 more sources
Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms [PDF]
International Journal of Computational Intelligence Systems, 2011 This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT) suitable for electronic warfare (EW) applications.
He Chen +3 more
doaj +1 more source
Statistical lossless compression of space imagery and general data in a reconfigurable architecture [PDF]
, 2008 This paper investigates an universal algorithm and hardware architecture for context-based statistical lossless compression of multiple types of data using FPGA (Field Programmable Gate Array) devices which support partial and dynamic reconfiguration ...
Canagarajah, CN +3 more
core +2 more sources
Implementation of fractional order integrator/differentiator on field programmable gate array
Alexandria Engineering Journal, 2016 Concept of fractional order calculus is as old as the regular calculus. With the advent of high speed and cost effective computing power, now it is possible to model the real world control and signal processing problems using fractional order calculus ...
K.P.S. Rana +3 more
doaj +1 more source
A high performance cost-effective digital complex correlator for an X-band polarimetry survey [PDF]
, 2016 The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals.
Barbosa, Domingos +7 more
core +2 more sources
Design of Novel Field Programmable Gate Array-Based Hearing Aid
IEEE Access, 2019 Hearing loss is one of the most common chronic diseases. For people with hearing loss, communicating with other people, particularly in an environment with considerable background noise, is difficult. Recently, several hearing aids have been developed to
Bor-Shing Lin +5 more
doaj +1 more source
The Journal of Engineering, 2019 This study proposes an implementation based on a low-cost field-programmable gate array (FPGA) of a high-resolution pulse width modulation applied on a single-phase power factor correction (PFC) converter operating with 2 MHz switch frequency.
José Augusto Arbugeri +2 more
doaj +1 more source
Implementation of the block cipher Rijndael using Altera FPGA
Journal of Telecommunications and Information Technology, 2001 A short description of the block cipher Rijndael is presented. Hardware implementation by means of the FPGA (field programmable gate array) technology is evaluated. Im- plementation results compared with other hardware imple- mentations are summarized.
Piotr Mroczkowski
doaj +1 more source
Implemetasi Komputasi Akar Kuadrat Resolusi Tinggi pada Field Programmable Gate Array (FPGA)
Jurnal Teknologi Informasi dan Ilmu Komputer, 2022 Komputasi akar kuadrat diperlukan pada beberapa proses pengendalian, diantaranya untuk Direct Torque Control (DTC) pada sistem penggerak motor yang membutuhkan proses perhitungan yang sangat cepat.
Muhammad Irfan, Hendra Setiawan
doaj +1 more source
Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications [PDF]
, 2007 Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from benefits of rapid prototyping.
Daud, Taher +4 more
core +1 more source