Results 51 to 60 of about 71,483 (292)

A Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Arrays [PDF]

, 2007
An artificial neural network algorithm is implemented using a field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time ...
Badala, Boos, Denby, E. Won, Eide, Haas, Hakl, Hertz, Köhne, Leimgruber, Prevotet   +10 more
core   +2 more sources

Imaging of Biphoton States: Fundamentals and Applications

Advanced Functional Materials, EarlyView.
Quantum states of two photons exhibit a rich polarization and spatial structure, which provides a fundamental resource of strongly correlated and entangled states. This review analyzes the physics of these intriguing properties and explores the various techniques and technologies available to measure them, including the state of the art of their ...
Alessio D'Errico, Ebrahim Karimi
wiley   +1 more source

InSight: An FPGA-Based Neuromorphic Computing System for Deep Neural Networks

Journal of Low Power Electronics and Applications, 2020
Deep neural networks have demonstrated impressive results in various cognitive tasks such as object detection and image classification. This paper describes a neuromorphic computing system that is designed from the ground up for energy-efficient ...
Taeyang Hong, Yongshin Kang, Jaeyong Chung   +2 more
doaj   +1 more source

Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices [PDF]

, 2018
A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to ...
Białas, P., Curceanu, C., Czerwiński, E., Dulski, K., Flak, B., Gajos, A., Gorgol, M., Głowacz, B., Hiesmayr, B. C., Jasińska, B., Kacprzak, K., Kajetanowicz, M., Kisielewska, D., Korcyl, G., Kowalski, P., Kozik, T., Krawczyk, N., Krzemień, W., Kubicz, E., Mohammed, M., Moskal, P., Niedźwiecki, Sz., Pawlik-Niedźwiecka, M., Pałka, M., Raczyński, L., Rajda, P., Rudy, Z., Salabura, P., Sharma, N. G., Sharma, S., Shopa, R. Y., Silarski, M., Skurzok, M., Strzempek, P., Wieczorek, A., Wiślicki, W., Zaleski, R., Zgardzińska, B., Zieliński, M.   +38 more
core   +2 more sources

Peptide Mass Fingerprinting Using Field-Programmable Gate Arrays [PDF]

IEEE Transactions on Biomedical Circuits and Systems, 2009
The reconfigurable computing paradigm, which exploits the flexibility and versatility of field-programmable gate arrays (FPGAs), has emerged as a powerful solution for speeding up time-critical algorithms. This paper describes a reconfigurable computing solution for processing raw mass spectrometric data generated by MALDI-TOF instruments. The hardware-
Bogdan, I.A., Coca, D., Beynon, R.J.
openaire   +3 more sources

Unraveling Quantitative Sensing Mechanism and Predictive Molecular Metrics for High‐Performance OFET Amine Sensors

Advanced Functional Materials, EarlyView.
This study introduces a novel chloro boron subphthalocyanine/polymer blend OFET sensor achieving 0.005 ppb limit of detection for ammonia at room temperature and high selectivity against similar amines. An original theoretical framework is proposed to describe the sensing mechanism, relating analyte molecular volume and Lewis basicity to sensor ...
Kavinraaj Ella Elangovan, Matthew P. Confer, Rui Zhang, Siqing Wang, Jeffrey S. Moore, Rohit Bhargava, Ying Diao   +6 more
wiley   +1 more source

Ultrafast jet classification at the HL-LHC

Machine Learning: Science and Technology
Three machine learning models are used to perform jet origin classification. These models are optimized for deployment on a field-programmable gate array device.
Patrick Odagiu, Zhiqiang Que, Javier Duarte, Johannes Haller, Gregor Kasieczka, Artur Lobanov, Vladimir Loncar, Wayne Luk, Jennifer Ngadiuba, Maurizio Pierini, Philipp Rincke, Arpita Seksaria, Sioni Summers, Andre Sznajder, Alexander Tapper, Thea K Årrestad   +15 more
doaj   +1 more source

Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

IEEE Access, 2019
Phasor Measurement Units (PMUs) are becoming intrinsic components of modern power systems. The synchrophasor estimation algorithms in PMUs pose stringent computational demands, which makes the application of Field Programmable Gate Arrays (FPGA) highly ...
Prottay M. Adhikari, Hossein Hooshyar, Luigi Vanfretti   +2 more
doaj   +1 more source

Integration of Low‐Voltage Nanoscale MoS2 Memristors on CMOS Microchips

Advanced Functional Materials, EarlyView.
This article presents the first monolithic integration of nanoscale MoS2‐based memristors into the back‐end‐of‐line of foundry‐fabricated CMOS microchips in a one‐transistor‐one‐resistor (1T1R) architecture. The MoS2‐based 1T1R cells exhibit forming‐free, nonvolatile resistive switching with ultra‐low operating voltages, low cycle‐to‐cycle variability ...
Jimin Lee, Sofía Cruces, Xiaohua Liu, Yang Chen, Vasilis A. Maroufidis, Janghyun Jo, Lukas Völkel, Dennis Braun, Michael Möller, Leon Brackmann, Holger Kalisch, Michael Heuken, Andrei Vescan, Rafal E. Dunin‐Borkowski, Joachim Mayer, Stefan Wiefels, Max C. Lemme   +16 more
wiley   +1 more source

Implementation of Reed-Solomon Encoder/Decoder Using Field Programmable Gate Array

Journal of Engineering and Sustainable Development, 2006
In this paper, (15, 11) and (255, 239) Reed-Solomon codes have been designed and Implemented using ALTERA Field Programmable Gate Array (FPGA) device. The design is carried out by writing VHDL modules for different encoder and decoder components.
Hikmat N. Abdullah
doaj