Results 181 to 190 of about 46,893 (234)

Design issues in field programmable gate arrays (FPGAs)

ICM'99. Proceedings. Eleventh International Conference on Microelectronics (IEEE Cat. No.99EX388), 2000
In this paper, we present some of the important design factors and performance issues in the development of field programmable gate arrays (FPGAs). Emphasis is placed on the design of logic blocks and interconnection resources. We also discuss the possibility of using multiple-valued logic in the design of FPGA logic blocks.
M. Abd-El-Barr, Z. Vranesic
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Field programmable gate arrays (FPGAs)

1997
For FPGAs, the variety of architectures is larger as each manufacturer develops concepts for particular niche markets and this, coupled with the non-deterministic nature of the timing for place and route, makes them more difficult to incorporate into designs.
R. C. Seals, G. F. Whapshott
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Field programmable gate array (FPGA) for iterative code evaluation

IEEE Transactions on Magnetics, 2006
Iterative codes such as low density parity check (LDPC) codes and turbo product codes (TPC) are of interest for data storage applications. To apply these codes to digital recording systems, two possible schemes are considered in this paper. In the first scheme, a single LDPC code of column weight j>2 is used to replace the Reed-Solomon (RS) code of the
null Lingyan Sun, null Hongwei Song, Z. Keirn, B.V.K.V. Kumar   +3 more
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Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

2004
Abstract : This report presents the results of research in the use of holographic modules in optoelectronic systems, their applications, and the characterization of polymer materials on which to record volume holograms for these modules. The first chapter makes the case that a direct interface between an optical memory and a chip integrating detectors ...
Demetri Psaltis, George Panotopoulos, Jose Mumbru   +2 more
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Clock Gating Implementation on commercial Field Programmable Gate Array (FPGA)

2018 4th International Conference on Electrical, Electronics and System Engineering (ICEESE), 2018
This paper discusses the application and implementation of clock gating technique to RISC32 (a customizable processor on Field Programmable Gate Array (FPGA)) for reduction of dynamic power consumption on clock tree. The FPGA used is Artix-7 (xc7a100tcsg324-1) from Xilinx with 28nm technology. The power consumption of clock tree is reduced by 24% after
Beng-Liong Tan, Wai-Kong Lee, Kai-Ming Mok, Hock-Guan Goh   +3 more
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Field programmable gate array (FPGA) based baseline JPEG decoder

2000 TENCON Proceedings. Intelligent Systems and Technologies for the New Millennium (Cat. No.00CH37119), 2002
Image/video compression is one of the major components used in video-telephony, videoconferencing and multimedia-related applications. Compression allows efficient utilization of channel bandwidth and/or storage size. One of the commonly used methods for image and video compression is JPEG (an image compression standard).
Z.M. Yusof, Z. Aspar, I. Suleiman
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Power Modelling in Field Programmable Gate Arrays (FPGA)

1999
This paper presents a power consumption model for FPGAs based on measurements. This model will permit us to optimize power consumption on FPGAs using existing architectures, as well as helping direct the design of new power-sensitive FPGA architectures.
Andrés Garcia, Wayne Burleson, Jean-Luc Danger   +2 more
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Field Programmable Gate Array (FPGA) Based IoT for Smart City Applications

2021
In the present era of modernization, automation and intelligent systems have become an integral part of our lives. These intelligent systems extremely rely on parallel computing technology for computation. Field Programmable Gate Arrays (FPGAs) have recently become extremely popular because of its reconfigurability. FPGA, an integrated circuit designed
Anvit Negi, Sumit Raj, Surendrabikram Thapa, S. Indu   +3 more
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Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)

Journal of The Institution of Engineers (India): Series B, 2014
In this work, a Built-in-Self-Test (BIST) technique has been proposed to detect crosstalk faults in FPGA and run time congestion and to provide the crosstalk aware router for FPGA. The proposed BIST circuits require less overhead as compared to earlier techniques. The proposed detector can detect any logic hazard or delay due to crosstalk.
N. Das, P. Roy, H. Rahaman
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Asynchronous field-programmable gate arrays (FPGAs)

2019
Field-programmable gate arrays (FPGAs) are chips that can be electronically programmed to function as an arbitrary digital circuit or system. They were originally used to replace discrete gates in interface electronics, and over the past three decades have evolved to being used in the place of application-specific integrated circuits (ASICs) in low ...
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