Results 61 to 70 of about 46,893 (234)
IEEE AccessAdvanced memory optimization techniques are reviewed to enhance the performance of Convolutional Neural Networks (CNNs) and Spiking Neural Networks (SNNs) on hardware accelerators, addressing the real-world challenges in medical imaging.
N. Srikanth Prasad, S. Sundar
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Implementation of Edge Detection Digital Image Algorithm on a FPGA
MATEC Web of Conferences, 2016 This paper presents the implementation of an adaptive contour detection filter on field programmable gate array (FPGA) using a combination of hardware and software components.
Bouganssa Issam +2 more
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FPGA as a tool for hardware realization of feedback control
Journal of Electrical Systems and Information Technology, 2015 The presented paper deals with the development of robust control algorithm based on reflection vectors methodology. This approach of controller design is guaranteeing stability, robustness and high performance.
Ján Cigánek +2 more
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An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes
, 2017 Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds ...
Chen, Ji +6 more
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A field programmable gate array based modular motion control platform [PDF]
, 2011 The expectations from motion control systems have been rising day by day. As the systems become more complex, conventional motion control systems can not achieve to meet all the specifications with optimized results.
Koc, Osman +5 more
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Review of Memristors for In‐Memory Computing and Spiking Neural Networks
Advanced Intelligent Systems, EarlyView.Memristors uniquely enable energy‐efficient, brain‐inspired computing by acting as both memory and synaptic elements. This review highlights their physical mechanisms, integration in crossbar arrays, and role in spiking neural networks. Key challenges, including variability, relaxation, and stochastic switching, are discussed, alongside emerging ...
Mostafa Shooshtari +2 more
wiley +1 more source
International Journal of Reconfigurable Computing, 2022 In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board.
Peter Jamieson +4 more
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Experimental 3D Asynchronous Field Programmable Gate Array (FPGA) [PDF]
, 2015 Abstract : 3D technology has the potential to significantly enhance the capabilities of a computing platform through tight integration of multiple levels of logic through low-cost vertical interconnects. The goal of this effort is to evaluate the potential of 3D technology in the context of an asynchronous Field Programmable Gate Array developed for ...
openaire +1 more source
Advanced Intelligent Systems, EarlyView.A fully integrated analog processing‐in‐memory system is demonstrated, combining charge‐trap flash synapse arrays with a successive integration‐and‐rescaling neuron circuit. The architecture performs bit‐sliced analog accumulation with high linearity and low power, achieving efficient and scalable analog in‐memory computing and bridging device‐level ...
Sojoong Kim +4 more
wiley +1 more source
Implementation of a Recursive Data of Adaptive QRD-RIS Algorithm Using HDI Coder
Journal of Engineering and Sustainable Development, 2013 Matrix inversion is a common function found in many algorithms used in wireless communication systems. As Field Programmable Gate Array (FPGA) become an increasingly attractive platform for wireless communication, it is important to understand the ...
Ali Khalid Jassim +2 more
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