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Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review

Journal of Nanoelectronics and Optoelectronics, 2019
With the increasing number of electronic consumer and information technology, demands for non-volatile memory rapidly grow. This study comprehensively reviewed the challenges related to the floating gate transistor for each component of the gate stack ...
Michael Loong Peng Tan, Razali Ismail, Tan Michael Loong Peng   +2 more
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Reversible floating-gate memory

Journal of Applied Physics, 1973
Reversible memory behavior is reported for an insulated gate structure, in which charge is stored on a polysilicon gate. This gate is floating between layers of silicon dioxide (SiO2) and silicon nitride (Si3N4). The floating gate is charged negatively by hot carrier injection through the SiO2, from an avalanche plasma in the underlying silicon.
H. C. Card, A. G. Worrall
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A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories

2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL), 2021
Consumer demands are outgrowing the benefits of technology scaling, especially for binary circuits. Previous studies proposed multi-valued logic (MVL) architectures, but these architectures use non-standard fabrication techniques and optimistic performance analysis.
Ayokunle Fadamiro, Pouyan Rezaie, Spencer K. Millican, Christoper B. Harris   +3 more
openaire   +1 more source

Floating gate memories reliability

Quality and Reliability Engineering International, 1992
AbstractBesides conventional IC failure mechanisms, the floating gate (FG) device reliability is affected by data retention, characteristic of non‐volatile memories, and endurance, typical of electrically erasable arrays.The subjects of this work are EPROM and flash EEPROM, the leading and most promising devices among the FG non‐volatile memories.The ...
G. Crisenza, C. Clementi, G. Ghidini, M. Tosi   +3 more
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Radiation effects on floating-gate memory cells

IEEE Transactions on Nuclear Science, 2001
We have addressed the problem of threshold voltage (V/sub TH/) variation in flash memory cells after heavy-ion irradiation by using specially designed array structures and test instruments. After irradiation, low V/sub TH/ tails appear in V/sub TH/ distributions, growing with ion linear energy transfer (LET) and fluence.
CELLERE G., PELLATI P., CHIMENTON A., WYSS, JEFFERY, MODELLI A., LARCHER L., PACCAGNELLA A.   +6 more
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Transparent nano-floating gate memory on glass

Nanotechnology, 2010
We construct fully transparent nano-floating gate memory devices on a glass substrate. These memory thin-film transistors consist of channel layers of ZnO films, electrodes of Al/ITO, and floating gate nodes of Al nanoparticles, exhibiting a transmittance of approximately 71% in the visible region.
Byoungjun, Park, Kyoungah, Cho, Sungsu, Kim, Sangsig, Kim   +3 more
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Layer‐by‐Layer‐Assembled Reduced Graphene Oxide/Gold Nanoparticle Hybrid Double‐Floating‐Gate Structure for Low‐Voltage Flexible Flash Memory

Advanced Materials, 2013
A hybrid double-floating-gate flexible memory device by utilizing an rGO-sheet monolayer and a Au NP array as upper and lower floating gates is reported. The rGO buffer layer acts as a charge-trapping layer and introduces an energy barrier between the Au
Su-Ting Han, Ye Zhou, Chundong Wang
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Nanoparticle floating gate flash memories

Conference Digest [Late News Papers volume included]Device Research Conference, 2004. 62nd DRC., 2004
This work presents the use of SiGe nanoparticle floating gates on high-k gate tunneling dielectrics, which, along with SiGe cold cathodes in the channel, are ways to enhance the low voltage/power operation of flash cells, improve the speed and charge retention. Control of dot sizes and spatial distributions may be improved by templated growth.
S. Banerjee, D. Kim, T. Kim, L. Weltzer, Y. Liu, S. Tang, M. Palard   +6 more
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Floating gate memory paper transistor

SPIE Proceedings, 2010
Reported herein is a nonvolatile n-type floating gate memory paper field-effect transistor, emphasizing the role of the paper structure and properties on the device performance recorded such as in the high capacitance per unit area at low frequencies (>2.5 μFcm -2 ) and so on the set of high charge retention times achieved (>16000 hours).
R. Martins, L. Pereira, P. Barquinha, N. Correia, G. Gonçalves, I. Ferreira, C. Dias, E. Fortunato   +7 more
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A Quaternary FPGA Architecture Using Floating Gate Memories

2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2020
A new quaternary FPGA (QFPGA) architecture based on floating-gate memories is presented and analyzed. Technology scaling has delivered substantial FPGA performance, but consumer demands grow beyond binary circuit capabilities. Non-binary FPGAs have been explored, but previous architectures use non-standard fabrication and optimistic performance ...
Ayokunle Fadamiro, Pouyan Rezaie, Christopher Harris, Spencer K. Millican   +3 more
openaire   +1 more source