Results 261 to 270 of about 4,902 (297)

Hierarchical Constrained Coding for Floating-Gate to Floating-Gate Coupling Mitigation in Flash Memory

2011 IEEE Global Telecommunications Conference - GLOBECOM 2011, 2011
Flash memory comprises of grid of cells arranged in a rectangular lattice. A cell is a floating gate and the information is stored as charge in these floating gates. A multi-level-cell (MLC) can store more than one bit per cell. An ideal programming of a cell consists of injecting just the correct amount of charge in the cell by hot-electron injection.
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A floating-gate memory cell for continuous-time programming

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012
As an apt choice for long-term analog memory in standard CMOS processes, floating-gate transistors are key enablers for large-scale programmable analog systems. Such systems are often designed for battery-powered—and generally resource-constrained—applications, which require the memory cells to program quickly with low infrastructural overhead.
Brandon Rumberg, David W. Graham
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Gate Bridge to Drain Contact Characteristic in Floating Gate Memory

International Symposium for Testing and Failure Analysis, 2013
Abstract Gate-to-drain contact short issue in floating gate memory has been studied. Two cases will be discussed, floating-gate to drain contact short, and control-gate to drain contact short, both caused by leakage bridge defect. The abnormal electrical device characteristic combined with modeling gives further insight into the failure ...
Pei Wei Chiang, Yu Ting Ling, Bo Chih Chen, Hsiao Tien Chang   +3 more
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Device Simulations in Coupled Floating-Gate Memories

Japanese Journal of Applied Physics, 2005
Two device simulations were carried out to investigate the possibilities of nano sized floating-gate memories. In the first simulation, we calculated the characteristics of coupled floating-gate devices based on a conventional simulator. We found that the memory performance is improved by coupling two floating gates.
Tetsufumi Tanamoto, Ryuji Ohba, Shin-ichi Yasuda, Keiko Abe, Shinobu Fujita   +4 more
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Floating Gate Flash Memories

2009
This chapter contains sections titled: Introduction Basics of Program and Erase Operations Flash Memories with Channel Hot-Electron (CHE) Program and Tunnel Oxide Erase Flash Memories with Channel Hot-Electron Program and Poly-To-Poly Erase Flash Memories with Fowler-Nordheim Tunnel Program and Erase Special and ...
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A floating gate and its application to memory devices

IEEE Transactions on Electron Devices, 1967
A structure has been proposed and fabricated in which semipermanent charge storage is possible. A floating gate is placed a small distance from an electron source. When an appropriately high field is applied through an outer gate, the floating gate charges up.
K. Kahng, S.M. Sze
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Ge ∕ Si heteronanocrystal floating gate memory

Applied Physics Letters, 2007
Metal oxide semiconductor field effect transistor memories with Ge∕Si heteronanocrystals (HNCs) as floating gate were fabricated and characterized. Ge∕Si HNCs with density of 5×1011cm−2 were grown on n-type Si (100) substrate with thin tunnel oxide on the top.
Bei Li, Jianlin Liu, G. F. Liu, J. A. Yarmoff   +3 more
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A nonvolatile ferroelectric memory device with a floating gate

Applied Physics Letters, 1996
An adaptive ferroelectric field-effect transistor (FET) with a floating gate has been developed using a thin film of lead titanate ( PbTiO3) deposited on a n/p+ substrate by rf sputtering. This device utilizes the charge storage on the floating gate to control the n layer conductivity of a n/p+ Si substrate and performs a memory function, in which the ...
F. Y. Chen, Y. K. Fang, M. J. Sun, Jiann-Ruey Chen   +3 more
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Back-floating gate non-volatile memory

2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 2005
Conventional floating-gate flash memory has scaling difficulties due to nonscaling of gate-insulator stack and inefficient hot carrier injection processes at sub-50 nm gate dimensions. Back-floating gate (BFG) flash memory structure overcomes these limitations by decoupling read and write operation and independent positioning and/or sizing of the ...
U. Avci, A. Kumar, S. Tiwari
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Floating-Gate a-Si:H TFT Nonvolatile Memories

MRS Proceedings, 2008
ABSTRACTCharge and discharge phenomena of the floating-gate amorphous silicon thin film transistor have been studied under dynamic operation conditions. The charge storage capacity decreases with the increase of the drain voltage because it is easier for electrons to be transported to the drain electrode than to be injected into the gate dielectric ...
Yue Kuo, Helinda Nominanda
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