Results 101 to 110 of about 384,291 (294)
Multichannel FPGA based MVT system for high precision time (20~ps~RMS) and charge measurement
In this article it is presented an FPGA based $M$ulti-$V$oltage $T$hreshold (MVT) system which allows of sampling fast signals ($1-2$ ns rising and falling edge) in both voltage and time domain.
Bednarski, T. +31 more
core +1 more source
A biomimetic fiber‐entangled island architecture is proposed to address the stress concentration issues commonly observed in conventional island arrays. Based on this architecture, a pressure‐sensing e‐skin with simultaneously high spatial resolution, low strain interference, and excellent permeability is developed, which is further applied to wearable
Ruixiang Qu +11 more
wiley +1 more source
Research on Resistive Switching Mechanism of SnO2/SnS2 Based Heterojunction Memory Devices
This work fabricates SnO2/SnS2 RRAM using (NH4)4Sn2S6, achieving 224 pJ set energy at 0.4 V with >1000‐cycle stability and 4 × 104 s retention. XPS/SEM/AFM‐validated interfacial engineering enables uniform switching, advancing low‐power neuromorphic memory development.
WenBin Liu +4 more
wiley +1 more source
4K-supporting ARINC818 video transporting and verifying system
In demand of 4K or higher resolution video transporting in cockpit in the future, a common system related to ARINC818 video codec is referred and verified through DP video port in this article.
Gao Weilin, Yang Bingwei, Xin Chunming
doaj +1 more source
The properties and data structure of distance histogram algorithm of three-dimensional space data were analyzed, and a general computing method based on graphics processor and a high performance computing method based on FPGA were proposed.
PEI Hao, YOU Xiaorong, NIU Xinwei
doaj +1 more source
Using FPGA for visuo-motor control with a silicon retina and a humanoid robot [PDF]
The address-event representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. The event information is transferred using a high speed digital parallel bus.
Delbrück, T. +4 more
core
A diagnostic method for reconfigurable intelligent surfaces (RIS) based on non‐uniform space‐time‐coding modulation is presented. Fault localization is achieved via amplitude‐only spectral measurements, eliminating the need for complex signal processing. A one‐to‐one mapping between harmonic components and RIS elements enables accurate detection.
Xiao Qing Chen +8 more
wiley +1 more source
Design of a novel transmission circuit of transient electromagnetic instrument
A transmission circuit of transient electromagnetic instrument based on FPGA was designed in order to improve measurement accuracy of transient electromagnetic instrument. Drive circuit of the transmission circuit was designed with module EXB841 to drive
XU Yakun +3 more
doaj +1 more source
This paper reviews the physics of liquid metals in RF devices, including the influence of mechanical strain on resonance as well as fabrication methods and strategies for designing tunable and strain‐tolerant inductors, capacitors, and antennas.
Md Saifur Rahman, William J. Scheideler
wiley +1 more source
Implementation of Multi-Core Processor Based on PLASMA (most MIPS I) IP Core
Multi-core processors is a design philosophy that has become mainstream in scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices has permitted complex logic systems to be implemented on a single ...
Bojan Gruevski +2 more
doaj +1 more source

