Results 201 to 210 of about 173,842 (233)

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Proceedings of the 2009 ACM SIGMOD International Conference on Management of data, 2009
The subject of this thesis the design of a dual processor system and the development of the jpeg algorithm on them. The system was implemented on a Xilinx Spartan 3E. Every tool used either hardware (Spartan 3E Starter Kit Board) or software (EDK) are Xilinx products.
Rene Mueller, Jens Teubner
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FPGA Accelerated FPGA Placement

2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019
Placement is one of the runtime bottlenecks in an FPGA design implementation flow, in which global placement accounts for a major portion of the runtime. In this paper, we demonstrate FPGA acceleration of wirelength gradient computation, which is an important part of modern analytical placement tools.
Shounak Dhar, Love Singhal, Mahesh Iyer, David Pan   +3 more
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FPGAs

Proceedings of the 13th International Conference on Extending Database Technology, 2010
In line with the insight that "one size" of databases will not fit all application needs [19] the database community is currently exploring various alternatives to commodity, CPU-based system designs. One particular candidate in this trend are field-programmable gate arrays (FPGAs), programmable chips that allow tailor-made hardware designs optimized ...
Rene Mueller, Jens Teubner
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2013
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2014
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FPGA

2010
The method of Moore FSM as a Petri network on FPGA is offered. The method is based on the flow-chart transformation to a Petri network with its realization as principal circuit. The features of the Moore FSM circuit realization on FPGA are considered and the method of its synthesis on the base of flow-chart is offered.
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Hybrid FPGA Architecture

Fourth International ACM Symposium on Field-Programmable Gate Arrays, 1996
This paper proposes a new field-programmable architecture that is a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PALs/PLAs. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large ...
Alireza Kaviani, Stephen Brown
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FPGA-Assisted Deterministic Routing for FPGAs

2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2019
FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compiletest cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi-CPU platforms. Instead, we propose porting FPGA routing to a CPU+FPGA platform.
Dario Korolija, Mirjana Stojilovic
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2014

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