Results 201 to 210 of about 165,505 (261)

An all-digital RF transmitter architecture based on jitter-enhanced PWM for flexible frequency applications. [PDF]

Sci Rep
Long B, Chen W, Hu Z, Bai Y, Liu D, Liu H.   +5 more
europepmc   +1 more source

Dynamics Research of the Hopfield Neural Network Based on Hyperbolic Tangent Memristor with Absolute Value. [PDF]

Micromachines (Basel)
Gao H, Xu H.
europepmc   +1 more source

Conformal Radiation-Type Programmable Metasurface for Agile Millimeter-Wave Orbital Angular Momentum Generation. [PDF]

Research (Wash D C)
Cao A, Ni T, Chen Y, Wang L, Li Z, Bai X, Zhang F, Chen Z.   +7 more
europepmc   +1 more source

Borehole Radar Experiment in a 7500 m Deep Well. [PDF]

Sensors (Basel)
Yang H, Wang K, Liu Y, Guo C, Zhao Q.
europepmc   +1 more source

Realizing the Calculation of a Fully Normalized Associated Legendre Function Based on an FPGA. [PDF]

Sensors (Basel)
Fang Y, Wang Q, Yang Y.
europepmc   +1 more source

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The Future of FPGA Acceleration in Datacenters and the Cloud

ACM Transactions on Reconfigurable Technology and Systems, 2022
In this article, we survey existing academic and commercial efforts to provide Field-Programmable Gate Array (FPGA) acceleration in datacenters and the cloud.
C. Bobda, Joel Mandebi Mbongue, P. Chow, M. Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, M. Leeser, M. Herbordt, Hafsah Shahzad, Peter Hofste, Burkhard Ringlein, Jakub Szefer, A. Sanaullah, R. Tessier   +16 more
semanticscholar   +1 more source

FPGA Architecture: Principles and Progression

IEEE Circuits and Systems Magazine, 2021
Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster
Andrew Boutros, Vaughn Betz
semanticscholar   +1 more source

FPGA Accelerated FPGA Placement

2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019
Placement is one of the runtime bottlenecks in an FPGA design implementation flow, in which global placement accounts for a major portion of the runtime. In this paper, we demonstrate FPGA acceleration of wirelength gradient computation, which is an important part of modern analytical placement tools.
Shounak Dhar, David Z. Pan, Mahesh A. Iyer, Love Singhal   +3 more
openaire   +2 more sources

FTRANS: energy-efficient acceleration of transformers using FPGA

International Symposium on Low Power Electronics and Design, 2020
In natural language processing (NLP), the "Transformer" architecture was proposed as the first transduction model replying entirely on self-attention mechanisms without using sequence-aligned recurrent neural networks (RNNs) or convolution, and it ...
Bingbing Li, Santosh Pandey, Haowen Fang, Yanjun Lyv, Ji Li, Jieyang Chen, Mimi Xie, Lipeng Wan, Hang Liu, Caiwen Ding   +9 more
semanticscholar   +1 more source