Results 221 to 230 of about 165,505 (261)

TRACER-fpga: a router for RAM-based FPGA's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
We describe a routing method for the design of a class of RAM-based field programmable gate arrays (FPGA). We model the interconnect resources as a graph. A routing solution is represented as a set of disjoint trees, each connecting all terminals of a net, on the graph. An expansion router is used for connecting a net.
Youn-Long Lin, Yuh-Sheng Lee, Allen C.-H. Wu, Ching-Dong Chen   +3 more
openaire   +1 more source

Crosstalk noise in FPGAs [PDF]

Proceedings of the 40th annual Design Automation Conference, 2003
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem affecting circuit reliability. Even though FPGAs are more immune to crosstalk noise than their ASIC counterparts manufactured in the same technological process, we have reached ...
Malgorzata Marek-Sadowska, Yajun Ran
openaire   +1 more source

Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity

Symposium on Field Programmable Gate Arrays, 2019
Neural networks based on Long Short-Term Memory (LSTM) are widely deployed in latency-sensitive language and speech applications. To speed up LSTM inference, previous research proposes weight pruning techniques to reduce computational cost. Unfortunately,
Shijie Cao, Chen Zhang, Zhuliang Yao, Wencong Xiao, Lanshun Nie, D. Zhan, Yunxin Liu, Ming Wu, Lintao Zhang   +8 more
semanticscholar   +1 more source

DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020
Existing FPGA-based DNN accelerators typically fall into two design paradigms. Either they adopt a generic reusable architecture to support different DNN networks but leave some performance and efficiency on the table because of the sacrifice of design ...
Xiaofan Zhang, Hanchen Ye, Junsong Wang, Yonghua Lin, Jinjun Xiong, Wen-mei W. Hwu, Deming Chen   +6 more
semanticscholar   +1 more source

Programming FPGAs---Programming FPGAs

Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC '06, 2006
The use of FPGAs for general-purpose supercomputing is being investigated by several projects worldwide. The FPGA High Performance Computing Alliance (FHPCA) is developing HPC solutions for real-world applications using FPGAs. It has built a 64-FPGA supercomputer located in Scotland.The widespread take-up of FPGAs will only occur when they are more ...
Mark I Parsons, Francis W Wray
openaire   +2 more sources

FPGA/DNN Co-Design: An Efficient Design Methodology for 1oT Intelligence on the Edge

Design Automation Conference, 2019
While embedded FPGAs are attractive platforms for DNN acceleration on edge-devices due to their low latency and high energy efficiency, the scarcity of resources of edge-scale FPGA devices also makes it challenging for DNN deployment.
Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, K. Rupnow, Wen-mei W. Hwu, Deming Chen   +7 more
semanticscholar   +1 more source

[DL] A Survey of FPGA-based Neural Network Inference Accelerators

ACM Transactions on Reconfigurable Technology and Systems, 2019
Recent research on neural networks has shown a significant advantage in machine learning over traditional algorithms based on handcrafted features and models.
Kaiyuan Guo, Shulin Zeng, Jincheng Yu, Yu Wang, Huazhong Yang   +4 more
semanticscholar   +1 more source

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud

International Symposium on Computer Architecture, 2018
We present FireSim, an open-source simulation platform that enables cycle-exact microarchitectural simulation of large scale-out clusters by combining FPGA-accelerated simulation of silicon-proven RTL designs with a scalable, distributed network ...
S. Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, B. Nikolić, R. Katz, J. Bachrach, K. Asanović   +15 more
semanticscholar   +1 more source

Hybrid FPGA Architecture

Fourth International ACM Symposium on Field-Programmable Gate Arrays, 1996
This paper proposes a new field-programmable architecture that is a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PALs/PLAs. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large ...
Alireza S. Kaviani, Stephen J. Brown
openaire   +2 more sources

A Hypervisor for Shared-Memory FPGA Platforms

International Conference on Architectural Support for Programming Languages and Operating Systems, 2020
Cloud providers widely deploy FPGAs as application-specific accelerators for customer use. These providers seek to multiplex their FPGAs among customers via virtualization, thereby reducing running costs.
Jiacheng Ma, Gefei Zuo, Kevin Loughlin, Xiao-he Cheng, Yanqiang Liu, Abel Mulugeta Eneyew, Zhengwei Qi, Baris Kasikci   +7 more
semanticscholar   +1 more source