Results 221 to 230 of about 384,291 (294)

A survey of FPGA-based accelerators for convolutional neural networks

Neural Computing and Applications, 2018
Sparsh Mittal
exaly   +2 more sources

FP-BNN: Binarized neural network on FPGA

Neurocomputing, 2018
Shuang Liang, Leibo Liu, Wayne Luk
exaly   +2 more sources

The Future of FPGA Acceleration in Datacenters and the Cloud

ACM Transactions on Reconfigurable Technology and Systems, 2022
In this article, we survey existing academic and commercial efforts to provide Field-Programmable Gate Array (FPGA) acceleration in datacenters and the cloud.
C. Bobda, Joel Mandebi Mbongue, P. Chow, M. Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, M. Leeser, M. Herbordt, Hafsah Shahzad, Peter Hofste, Burkhard Ringlein, Jakub Szefer, A. Sanaullah, R. Tessier   +16 more
semanticscholar   +1 more source

FPGA Architecture: Principles and Progression

IEEE Circuits and Systems Magazine, 2021
Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster
Andrew Boutros, Vaughn Betz
semanticscholar   +1 more source

FTRANS: energy-efficient acceleration of transformers using FPGA

International Symposium on Low Power Electronics and Design, 2020
In natural language processing (NLP), the "Transformer" architecture was proposed as the first transduction model replying entirely on self-attention mechanisms without using sequence-aligned recurrent neural networks (RNNs) or convolution, and it ...
Bingbing Li, Santosh Pandey, Haowen Fang, Yanjun Lyv, Ji Li, Jieyang Chen, Mimi Xie, Lipeng Wan, Hang Liu, Caiwen Ding   +9 more
semanticscholar   +1 more source

FPGA Accelerated FPGA Placement

2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019
Placement is one of the runtime bottlenecks in an FPGA design implementation flow, in which global placement accounts for a major portion of the runtime. In this paper, we demonstrate FPGA acceleration of wirelength gradient computation, which is an important part of modern analytical placement tools.
Shounak Dhar, David Z. Pan, Mahesh A. Iyer, Love Singhal   +3 more
openaire   +2 more sources

A flexible FPGA-to-FPGA communication system

2016 18th International Conference on Advanced Communication Technology (ICACT), 2016
In high-performance computing systems, each computing node communicates via a high-speed serial bus to ensure sufficient data transfer bandwidth. However, each computing node of different bus protocols is very difficult to communicate directly, which is not conducive to the extensibility of HPC (High performance computing) clusters.
An Wu, Xi Jin, ShuaiZhi Guo, XueLiang Du
openaire   +2 more sources

FPGA-Based Sensorless Speed Control of PMSM Using Enhanced Performance Controller Based on the Reduced-Order EKF

IEEE Journal of Emerging and Selected Topics in Power Electronics, 2021
In permanent magnet synchronous motor (PMSM) speed control, the PI closed-loop control model for current does exist. Although the standard PI closed-loop control has the basic tracking capability from the PMSM control system, however, the expected ...
Hong Yang, Ru Yang, Wei Hu, Zhenming Huang   +3 more
semanticscholar   +1 more source

DSSS with FPGA

2007 IEEE 15th Signal Processing and Communications Applications, 2007
In this paper, we present the implementation of Direct Sequence Spread Spectrum (DSSS) on Field Programmable Gate Array (FPGA) using one of the hardware definition languages ,Very High Speed Circuit Hardware Description Language (VHDL).AIgorithms are implemented on 3s100 evg100-4 device, belonging to Xlinx FPGA family.These systems are used in mobile ...
Ilker, Ethem Okan, Dincer, Hasan, Dikmese, Sener   +2 more
openaire   +3 more sources

FPGA-Assisted Deterministic Routing for FPGAs

2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2019
FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compiletest cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi-CPU platforms. Instead, we propose porting FPGA routing to a CPU+FPGA platform.
Dario Korolija, Mirjana Stojilovic
openaire   +1 more source