Results 31 to 40 of about 246,901 (236)
Architecture design of re-configurable convolutional neural network on software definition
网络与信息安全学报, 2021 In order to meet the flexibility and efficiency requirement in convolutional neural network (CNN), an architecture of re-configurable CNN based on software definition was proposed.
LI Peijie, ZHANG Li +1 more
doaj +1 more source
FMCW rail-mounted SAR: Porting spotlight SAR imaging from MATLAB to FPGA [PDF]
, 2014 In this work, a low-cost laptop-based radar platform derived from the MIT open courseware has been implemented. It can perform ranging, Doppler measurement and SAR imaging using MATLAB as the processor.
Gray, D., Le Kernec, J., Melnikov, A.
core +1 more source
Automatika, 2020 This paper discusses the hardware and control system design of the asymmetric cascade multilevel inverter. The asymmetric cascaded multilevel inverter structure is adopted to minimize bridges, gate drive circuits and DC power source number.
Lazhar Manai, Faouzi Armi, Mongi Besbes
doaj +1 more source
High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor
Technologies, 2020 Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures.
Argyrios Sideris +2 more
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Low-Power Pedestrian Detection System on FPGA
Proceedings, 2019 Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection.
Vinh Ngo +4 more
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FPGA-based heterogeneous acceleration study for multidimensional cubing [PDF]
ITM Web of Conferences, 2022 Today’s information processing not only faces an explosion of data volume and data dimensions, but also has to meet the growing user requirements for timeliness.
Meng Yuan, Yang Jun, Li Jun
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Motorcycle detection based on deep learning implemented on FPGA [PDF]
Songklanakarin Journal of Science and Technology (SJST), 2021 This paper proposes a hardware accelerator design for motorcycle detection based on deep learning. We designed the training parameters by K-means algorithm and created the motorcycle dataset from Thailand's urban scene.
Feng Peng +3 more
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SoPC-based DMA for PCI Express DAQ Cards [PDF]
International Journal of Electronics and Telecommunications, 2021 This paper presents low-cost, configurable PCI Express (PCIe) direct memory access (DMA) interface for implementation on Intel Cyclone V FPGAs. The DMA engine was designed to support DAQ tasks including pre-triggering acquisition for transient analysis ...
Krzysztof Mroczek
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Вестник Северо-Кавказского федерального университета, 2022 The purpose of the article is to study the possibility of compensating for the temperature instability of the quartz oscillator of an intelligent electronic device in case of loss of a synchronizing signal from a navigation satellite.An algorithm for ...
P. Zvada
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ParaFPGA 2011 : high performance computing with multiple FPGAs : design, methodology and applications [PDF]
, 2012 ParaFPGA 2011 marks the third mini-symposium devoted to the methodology, design and implementation of parallel applications using FPGAs. The focus of the contributions is mainly on organizing parallel applications in multiple FPGAs.
D'Hollander, Erik +2 more
core +2 more sources