Results 51 to 60 of about 246,901 (236)

Optimization on fixed low latency implementation of GBT protocol in FPGA

, 2016
In the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics.
Chen, Hucheng, Chen, Kai, Wu, Weihao, Xu, Hao, Yao, Lin   +4 more
core   +1 more source

FPGA-based conformance testing and system prototyping of an MPEG-4 SA-DCT hardware accelerator [PDF]

, 2005
Two FPGA implementations of a shape adaptive discrete cosine transform (SA-DCT) accelerator are presented in this paper: one PCI-based and the other AMBA-based. The former is used for conformance testing with the MPEG-4 standard requirements.
Casey, Alan, Kinane, Andrew, Muresan, Valentin, O'Connor, Noel E.   +3 more
core   +1 more source

A new approach for neural decoding by inspiring of hyperdimensional computing for implantable intra-cortical BMIs

Scientific Reports
In the field of Brain Machine Interface (BMI), the process of translating motor intention into a machine command is denoted as decoding. However, despite recent advancements, decoding remains a formidable challenge within BMI.
Danial Katoozian, Hossein Hosseini-Nejad, Mohammad-Reza A. Dehaqani   +2 more
doaj   +1 more source

Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL

Advances in Electrical and Electronic Engineering, 2012
This article describes the modelling and implementation of two different variants of direct frequency synthesizer, and evaluation of the performance of the finished design, in terms of memory and speed efficiency.
Daniel Kekrt, Milos Klima, Radek Podgorny, Jan Zavrtalek   +3 more
doaj   +1 more source

Technologies for implementing of artificial intelligence as a service based on hardware accelerators

Авіаційно-космічна техніка та технологія, 2022
The subject of study in this article is modern technologies, tools and methods of building AI systems as a service using FPGA as a platform. The goal is to analyze modern technologies and tools used to develop FPGA-based projects for systems that ...
Artem Perepelitsyn, Yelyzaveta Kasapien, Herman Fesenko, Vyacheslav Kharchenko   +3 more
doaj   +1 more source

Multichannel FPGA based MVT system for high precision time (20~ps~RMS) and charge measurement

, 2017
In this article it is presented an FPGA based $M$ulti-$V$oltage $T$hreshold (MVT) system which allows of sampling fast signals ($1-2$ ns rising and falling edge) in both voltage and time domain.
Bednarski, T., Białas, P., Czerwiński, E., Dulski, K., Gajos, A., Gorgol, M., Głowacz, B., Jasińska, B., Kajetanowicz, M., Kamińska, D., Korcyl, G., Kowalski, P., Kozik, T., Krzemień, W., Kubicz, E., Mohhamed, M., Moskal, P., Niedźwiecki, Sz., Pałka, M., Raczyński, L., Rudy, Z., Rundel, O., Salabura, P., Sharma, N. G., Silarski, M., Smyrski, J., Strzelecki, A., Strzempek, P., Wieczorek, A., Wiślicki, W., Zgardzińska, B., Zieliński, M.   +31 more
core   +1 more source

Survey of FPGA based recurrent neural network accelerator

网络与信息安全学报, 2019
Recurrent neural network(RNN) has been used wildly used in machine learning field in recent years, especially in dealing with sequential learning tasks compared with other neural network like CNN.
GAO Chen, ZHANG Fan
doaj   +1 more source

Throughput analysis for a high-performance FPGA-accelerated real-time search application [PDF]

, 2012
We propose an FPGA design for the relevancy computation part of a high-throughput real-time search application. The application matches terms in a stream of documents against a static profile, held in off-chip memory.
Chalamalasetti, S.R., Margala, M., Vanderbauwhede, W.   +2 more
core   +3 more sources

Estimación del estado de carga de una batería de litio con redes neuronales y validación con FPGA-en-lazo

Revista Iberoamericana de Automática e Informática Industrial RIAI
Los vehículos eléctricos presentan una alternativa viable para reducir las emisiones de gases tóxicos en las concentraciones urbanas y para disminuir los efectos de los gases de invernadero. La batería de los vehículos eléctricos debe ser monitoreada con
Erik Martínez-Vera, Alfredo Rosado-Muñoz, Pedro Bañuelos-Sánchez   +2 more
doaj   +1 more source

Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning

, 2017
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits.
Schmidt, Bernhard, Teich, Jürgen, Ziener, Daniel, Zöllner, Christian   +3 more
core   +2 more sources