Results 51 to 60 of about 196,878 (200)
Information, 2019 Orthogonal frequency division multiplexing (OFDM) has become an indispensable part of waveform generation in wideband digital communication since its first appearance in digital audio broadcasting (DAB) in Europe in 1980s, and it is indeed in use. As has
Somayeh Mohammady +3 more
doaj +1 more source
Enabling OpenMP Task Parallelism on Multi-FPGAs [PDF]
arXiv, 2021 FPGA-based hardware accelerators have received increasing attention mainly due to their ability to accelerate deep pipelined applications, thus resulting in higher computational performance and energy efficiency. Nevertheless, the amount of resources available on even the most powerful FPGA is still not enough to speed up very large modern workloads ...
arxiv
Mitigating RF jamming attacks at the physical layer with machine learning
IET Communications, Volume 17, Issue 1, Page 12-28, January 2023., 2023 Abstract Wireless communication devices must be protected from malicious threats, including active jamming attacks, due to the widespread use of wireless systems throughout our every‐day lives. Jamming mitigation techniques are predominately evaluated through simulation or with hardware for very specific jamming conditions.
Marko Jacovic +3 more
wiley +1 more source
Using an FPGA for Fast Bit Accurate SoC Simulation [PDF]
, 2007 In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required.
Hölzenspies, P.K.F. +2 more
core +2 more sources
IET Electrical Systems in Transportation, Volume 12, Issue 4, Page 298-314, December 2022., 2022 Abstract The computational efficiency is a challenging task in the real‐time implementation of battery State of Charge (SoC) estimation algorithms in Electric Vehicle (EV) application. This study proposes for the first time a pure hardware architecture of a Smooth Variable Structure Filter (SVSF) to estimate the SoC of a lithium‐ion battery in an EV ...
Sabeur Jemmali +2 more
wiley +1 more source
SVITE: A Spike-Based VITE Neuro-Inspired Robot Controller [PDF]
, 2013 This paper presents an implementation of a neuro-inspired algorithm called VITE (Vector Integration To End Point) in FPGA in the spikes domain. VITE aims to generate a non-planned trajectory for reaching tasks in robots. The algorithm has been adapted
Domínguez Morales, Manuel Jesús +4 more
core +1 more source
IET Power Electronics, Volume 16, Issue 1, Page 11-25, 7 January 2023., 2023 Abstract Recently, renewable distributed generation (DG) systems have emerged to improve the power system security and reliability while reducing the environmental incompatibility of fossil fuel power plants. DG could operate either as a standalone and/or as a grid‐connected power system. The interfacing circuits of DG and their controls have to comply
Alaa A. Mahmoud +5 more
wiley +1 more source
Predictive control using an FPGA with application to aircraft control [PDF]
, 2013 Alternative and more efficient computational methods can extend the applicability of MPC to systems with tight real-time requirements. This paper presents a “system-on-a-chip” MPC system, implemented on a field programmable gate array (FPGA), consisting ...
Constantinides, GA +5 more
core +1 more source
Unsupervised Recycled FPGA Detection Using Symmetry Analysis [PDF]
arXiv, 2023 Recently, recycled field-programmable gate arrays (FPGAs) pose a significant hardware security problem due to the proliferation of the semiconductor supply chain. Ring oscillator (RO) based frequency analyzing technique is one of the popular methods, where most studies used the known fresh FPGAs (KFFs) in machine learning-based detection, which is not ...
arxiv
A three‐phase three‐level converter with shared flying capacitors
IET Power Electronics, EarlyView., 2023 Three‐phase multilevel converters use a high number of components which increases their size. As specific weight reduction is a work of interest for embedded system applications, this paper presents a topology aiming to optimize volume and mass for a three‐level three‐phase inverter. The number of passive and active components is reduced thanks to the ‘
Maxime Pain +2 more
wiley +1 more source