Results 51 to 60 of about 173,842 (233)
Real‐Time 3D Ultrasound Imaging with an Ultra‐Sparse, Low Power Architecture
This article presents a novel, ultra‐sparse ultrasound architecture that paves the way for wearable real‐time 3D imaging. By integrating a unique convolutional array with chirped data acquisition, the system achieves high‐resolution volumetric scans at a fraction of the power and hardware complexity.
Colin Marcus +9 more
wiley +1 more source
Survey of FPGA based recurrent neural network accelerator
Recurrent neural network(RNN) has been used wildly used in machine learning field in recent years, especially in dealing with sequential learning tasks compared with other neural network like CNN.
GAO Chen, ZHANG Fan
doaj +1 more source
PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems [PDF]
We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs).
Fukushige, Toshiyuki +2 more
core +2 more sources
Combining high‐order cluster‐correlation expansion with experiment, it is revealed that P1‐driven NV decoherence under dynamical decoupling deviates from semi‐classical scaling laws. The coherence‐time exponent depends on pulse number and bath conditions, demonstrating the necessity of a full quantum bath description.
Huijin Park +8 more
wiley +1 more source
Los vehículos eléctricos presentan una alternativa viable para reducir las emisiones de gases tóxicos en las concentraciones urbanas y para disminuir los efectos de los gases de invernadero. La batería de los vehículos eléctricos debe ser monitoreada con
Erik Martínez-Vera +2 more
doaj +1 more source
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET
Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS
Gao Y. +11 more
core +1 more source
ParaFPGA 2011 : high performance computing with multiple FPGAs : design, methodology and applications [PDF]
ParaFPGA 2011 marks the third mini-symposium devoted to the methodology, design and implementation of parallel applications using FPGAs. The focus of the contributions is mainly on organizing parallel applications in multiple FPGAs.
D'Hollander, Erik +2 more
core +2 more sources
Spatial‐Wavelength Multiplexing Error‐Controlled Photonic Analog Computing System
A novel photonic integrated circuit prototype implementing the concept of general‐purpose analog computing and demonstrate its capability in radio frequency applications. The chip features a multichannel architecture and performs fully optical analog computation with frequency‐domain parallel processing. An FPGA‐based error‐correction algorithm aims to
Tao Zhu +15 more
wiley +1 more source
An on‐demand ultra‐reconfigurable intelligent vision system with hierarchical reconfigurability from device to system levels is demonstrated. Through co‐design of a multi‐paradigm device, reconfigurable circuits, and adaptive system architecture/algorithms, the system enables seamless switching among spiking, non‐spiking, neuromorphic imaging (NI), and
Biyi Jiang +7 more
wiley +1 more source
This paper is concerned with Field Programmable Gate Arrays (FPGA)-based systems for energy-efficient high-throughput string comparison. Modern applications which involve comparisons across large data sets—such as large sequence sets in molecular ...
Sarah Pilz +5 more
doaj +1 more source

