Results 81 to 90 of about 165,505 (261)
Survey of FPGA based recurrent neural network accelerator
Recurrent neural network(RNN) has been used wildly used in machine learning field in recent years, especially in dealing with sequential learning tasks compared with other neural network like CNN.
GAO Chen, ZHANG Fan
doaj +1 more source
Abstract This paper tackles the problem of robust and accurate fixed‐time tracking in human–robot interaction and deals with uncertainties. This work introduces a control approach for a wearable exoskeleton designed specifically for rehabilitation tasks.
Mahmoud Abdallah+4 more
wiley +1 more source
C3APSULe: Cross-FPGA Covert-Channel Attacks through Power Supply Unit Leakage
Field-Programmable Gate Arrays (FPGAs) are versatile, reconfigurable integrated circuits that can be used as hardware accelerators to process highly-sensitive data.
Ilias Giechaskiel+2 more
semanticscholar +1 more source
Low Overhead Online Data Flow Tracking for Intermittently Powered Non-volatile FPGAs [PDF]
Energy harvesting is an attractive way to power future IoT devices since it can eliminate the need for battery or power cables. However, harvested energy is intrinsically unstable. While FPGAs have been widely adopted in various embedded systems, it is hard to survive unstable power since all the memory components in FPGA are based on volatile SRAMs ...
arxiv
A consensus‐based adaptive hierarchical control strategy is designed for parallel ESUs in DC electrolytic hydrogen production systems to achieve rapid SoC balancing, proportional load current sharing, and stable bus voltage recovery. ABSTRACT With the expansion of off‐grid hydrogen production systems, the randomness and volatility of renewable energy ...
Yancheng Liu+6 more
wiley +1 more source
Method for Computing Dense Optical Flow on FPGA in Real Time
One of the most actual problems in the technical vision systems is the problem of objects detection and selection in the field of the image sensor view.
Alexander V. Bratulin+3 more
doaj +1 more source
This paper discusses the hardware and control system design of the asymmetric cascade multilevel inverter. The asymmetric cascaded multilevel inverter structure is adopted to minimize bridges, gate drive circuits and DC power source number.
Lazhar Manai, Faouzi Armi, Mongi Besbes
doaj +1 more source
For the series active filter (SAF), a combined controller and observer scheme is proposed. Two controllers—state feedback (SFB) and linear quadratic regulator (LQR)—along with state observers, including the Luenberger observer (LO), proportional–integral observer (PIO), and unknown input observer (UIO), have been designed.
Nagulapati Kiran, I. E. S. Naidu
wiley +1 more source
In this paper, we describe the complete architecture for quantum control and read‐out of charge qubits designed in 22‐nm FD‐SOI process. Detail system level analysis is provided along with lab measurement results at 3 K for cryogenic control and for a quantum dot array.
Imran Bashir+12 more
wiley +1 more source
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA [PDF]
As the emerging field of machine learning, deep learning shows excellent ability in solving complex learning problems. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses ...
Chao Wang+5 more
semanticscholar +1 more source