Results 91 to 100 of about 35,500 (242)

FPGA Implementation of Blob Recognition

2011 Canadian Conference on Computer and Robot Vision, 2011
Real-time embedded vision systems can be used in a wide range of applications and therefore the demand has been increasing for them. In this thesis, an FPGA-based embedded vision system capable of recognizing objects in real time is presented. The proposed system architecture consists of multiple Intellectual Properties (IPs), which are used as a set ...
Jian Xiong, Thanh Minh Nguyen, Q.M. Jonathan Wu   +2 more
openaire   +5 more sources

Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder

IEEE Access, 2019
Deep learning techniques have been gaining prominence in the research world in the past years; however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications.
Maria G. F. Coutinho, Matheus F. Torquato, Marcelo A. C. Fernandes   +2 more
doaj   +1 more source

Entropy‐Guided Convolutional Neural Network Classification of Sensor Signals for Real‐Time Surface Quality Monitoring in Direct Laser Interference Patterning

Advanced Intelligent Systems, EarlyView.
Neural‐network pipeline for real‐time DLIP surface‐quality monitoring: spectral entropy of WLI topographies is used to generate interpretable K‐means labels, which are transferred to time‐resolved photodiode traces. A compact dual‐input 1D‐CNN (signal + laser parameters) learns discriminative spatiotemporal features and predicts “OK/NOK” surface ...
Marcelo Daniel Sallese, Ignacio Tabares, Wei Wang, Marcos Soldera, Andrés Fabián Lasagni   +4 more
wiley   +1 more source

FPGA Implementations of Bireciprocal Lattice Wave Discrete Wavelet Filter Banks

Tikrit Journal of Engineering Sciences, 2012
In this paper, a special type of IIR filter banks; that is the bireciprocal lattice wave digital filter (BLWDF) bank, is presented to simulate scaling and wavelet functions of six-level wavelet transform.
Jassim M. Abdul-Jabbar, Sama N. M. Al-Faydi   +1 more
doaj   +3 more sources

FPGA Implementation of Vending Machine

Journal of VLSI Design and Signal Processing, 2023
This paper aims to create a coin processing system-based vending machine that can handle input coin values and dispense or return change as required, utilizing a single-state machine designed with the Mealy state machine model. To implement this design VHDL is used, which is a hardware description language capable of producing efficient and reliable ...
openaire   +1 more source

Wearable exoskeleton robot control using radial basis function‐based fixed‐time terminal sliding mode with prescribed performance

Asian Journal of Control, EarlyView.
Abstract This paper tackles the problem of robust and accurate fixed‐time tracking in human–robot interaction and deals with uncertainties. This work introduces a control approach for a wearable exoskeleton designed specifically for rehabilitation tasks.
Mahmoud Abdallah, Yassine Kali, Maarouf Saad, Raouf Fareh, Maamar Bettayeb   +4 more
wiley   +1 more source

Ultra‐High‐Efficiency On‐Chip CO2 Conversion by Nanosecond Self‐Pulsing Micro‐Plasma Devices

Carbon Energy, EarlyView.
A micro‐plasma chip with sub‐10‐μm electrode gaps is introduced for efficient CO2‐to‐CO conversion. The device self‐converts a DC power supply into nanosecond pulses, producing field‐emission electrons that vibrationally excite CO2, driving dissociation via the ladder‐climbing mechanism. A scaled‐up chip array achieves 30% single‐pass conversion and 50%
Guangyu Sun, Bartu Karakurt, Hongkeng Zhu, Onder Soydal, Jeremy S. Luterbacher, Elison Matioli   +5 more
wiley   +1 more source

Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

International Journal of Reconfigurable Computing, 2009
We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of ...
Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz   +4 more
doaj   +1 more source

FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

IEEE Access, 2019
Hardware implementation of the proposed direction of arrival (DOA) estimation algorithms based on Cholesky and LDL decomposition is presented in this paper.
Ahmed A. Hussain, Nizar Tayem, Abdel-Hamid Soliman, Redha M. Radaydeh   +3 more
doaj   +1 more source

A New Strategy to Design Reconfigurable Rivest–Shamir–Adleman (RSA) Accelerators

International Journal of Circuit Theory and Applications, EarlyView.
A reconfigurable FPGA‐based RSA accelerator is proposed using compression‐based modular multipliers combined with pseudomoduli arithmetic. The approach maps modular exponentiation to low‐cost arithmetic domains and applies a correction stage, achieving significant improvements in delay, operating frequency, and delay–area efficiency compared with ...
Augusto C. B. Vassoler, Gabriel B. M. Fernandes, Lucas R. Kieslich, Eduardo A. Bezerra, Hector Pettenghi   +4 more
wiley   +1 more source