Results 71 to 80 of about 35,500 (242)
High-Performance Architecture for Binary-Tree-Based Finite State Machines [PDF]
A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer
García Vargas, Ignacio +1 more
core
This paper reviews the physics of liquid metals in RF devices, including the influence of mechanical strain on resonance as well as fabrication methods and strategies for designing tunable and strain‐tolerant inductors, capacitors, and antennas.
Md Saifur Rahman, William J. Scheideler
wiley +1 more source
Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA [PDF]
This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system.
Alaoui Ismaili, Zine El Abidine +1 more
core +1 more source
A General and Efficient Framework for the Rapid Design of Miniaturized, Wideband, and High‐Bit RIS
A general and efficient framework is proposed for the rapid design of high‐performance reconfigurable intelligent surfaces (RISs). This framework integrates advanced antenna design techniques and incorporates various load types, quantities, and values to achieve the design of high‐performance RISs.
Jun Wei Zhang +14 more
wiley +1 more source
Terahertz Channel Modeling, Estimation and Localization in RIS‐Assisted Systems
Reconfigurable intelligent surfaces have become a recent intensive research focus. Based on practical applications, channel strategies for RIS‐assisted terahertz wireless communication systems are categorized into three different types: channel modeling, channel estimation, and channel localization.
Hongjing Wang +9 more
wiley +1 more source
Evaluating FPGA Acceleration with Intel ® oneAPI Toolkit for High-Speed Data Processing [PDF]
The LHCb Experiment employs GPU cards in its first level trigger system to enhance computing efficiency, achieving a data rate of 32 Tb/s from the detector.
Perro Alberto +3 more
doaj +1 more source
FPGA-based convolutional layer implementation
Abstract In this paper, several approaches to the implementation of a convolutional layer of a neural network on FPGAs for use in embedded systems are considered, as well as a number of optimizations necessary to speed up the operation of such a layer. At the end of the work, an FPGA-based implementation is proposed that is comparable in
A K Berzin, E S Dergunov
openaire +1 more source
RRAM Variability Harvesting for CIM‐Integrated TRNG
This work demonstrates a compute‐in‐memory‐compatible true random number generator that harvests intrinsic cycle‐to‐cycle variability from a 1T1R RRAM array. Parallel entropy extraction enables high‐throughput bit generation without dedicated circuits. This approach achieves NIST‐compliant randomness and low per‐bit energy, offering a scalable hardware
Ankit Bende +4 more
wiley +1 more source
A High performance and low cost hardware arcitecture for H.264 transform and quantization algorithms [PDF]
In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard.
Hamzaoglu, Ilker +3 more
core +1 more source
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley +1 more source

