Results 71 to 80 of about 289,843 (203)
ABSTRACT With the continuous development of computer image processing, developing efficient and low‐power computing devices has become a key challenge. Memristors have integrated in‐situ storage and computing capabilities, making them an ideal choice for low‐power image processing computing architectures. However, current memristors are confronted with
Tengyu Li +4 more
wiley +1 more source
Optimizations in Dynamic Binary Translation
We suggest using OpenCL standard for programming FPGA devices that are used as accelerators in a heterogeneous system. We describe the implementation of a subset of OpenCL that is required for organizing data exchange and task management for FPGAs given ...
Andrey Belevantsev +2 more
doaj
Efficient multi-standard cognitive radios on FPGAs [PDF]
Cognitive radios that support multiple standards and modify operation depending on environmental conditions are becoming more important as the demand for higher bandwidth and efficient spectrum use increases.
Pham, Thinh H. +5 more
core +1 more source
SPICE‐Compatible Compact Modeling of Cuprate‐Based Memristors Across a Wide Temperature Range
A physics‐guided compact model for YBCO memristors is introduced, incorporating carrier trapping, field‐induced detrapping, and a differential balance equation to describe their switching dynamics. The model is compared with experiments and implemented in LTspice, allowing realistic circuit‐level simulations.
Thomas Günkel +6 more
wiley +1 more source
Modern blockchain systems impose distinct cryptographic requirements, including pairing-based signatures for Ethereum, multi-scalar multiplication (MSM) for zero-knowledge proofs (ZKPs), and post-quantum migration, which existing hardware implementations
Ismail Ait Kaddour +2 more
doaj +1 more source
Evaluating FPGA Acceleration with Intel ® oneAPI Toolkit for High-Speed Data Processing [PDF]
The LHCb Experiment employs GPU cards in its first level trigger system to enhance computing efficiency, achieving a data rate of 32 Tb/s from the detector.
Perro Alberto +3 more
doaj +1 more source
Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs [PDF]
SRAM-based FPGAs are increasingly relevant in a growing number of safety-critical application fields, ranging from automotive to aerospace. These application fields are characterized by a harsh radiation environment that can cause the occurrence of ...
CASSANO, LUCA MARIA
core
Energy‐Aware Perturbation Optimization for Memristor‐Array Convolutional Neural Networks
Memristor‐array inference becomes more energy efficient when layer inputs are reshaped before computation. Sinusoidal perturbation encoding with dual‐threshold screening reduces active voltage pulses and contracts ADC input‐current ranges, jointly lowering crossbar and peripheral energy while preserving accuracy across hardware MNIST validation, deep ...
Ao Xu +6 more
wiley +1 more source
A Scalable and Resource‐Efficient Pipelined p‐Computer for Probabilistic Ising Machines
(a) Block diagram of the portfolio optimization problem: given M assets, the goal is to determine the optimal weights w that maximize the expected return (based on the mean historical assets return u), while minimizing the risk, quantified by the assets covariance matrix S.
Deborah Volpe +9 more
wiley +1 more source
Highly Versatile FPGA-Implemented Cyber Coherent Ising Machine
To solve large-scale real-world problems, attempts have been made to realize high-speed simulations of quantum Ising machines using field-programmable gate arrays (FPGAs) and to virtually realize networks with a large number of fully coupled spins, which
Toru Aonishi +7 more
doaj +1 more source

